Hello.
Welcome back.
So in this section we're going to learn about this serial peripheral interface which is known as SBA
for short.
Also another name for this serial powerful interface is the synchronous serial interface.
SS I for short so if you see SBI denoted us SS by it's the same thing.
SBA allows microcontrollers to communicate asynchronously with peripheral devices and other microcontrollers.
We can operate the SBA system as either master or slave.
Before we talk more about the SBA let's compare it to the new art and see the key differences.
The new art allows asynchronous communication and that is why it is called a universal asynchronous
receiver transmitter.
The SBA allows synchronous communication.
This means that to a device is communicating whether you are to operate the same frequency which we
call the default rate but have split but have separate clocks with you at the clock signal is not included
in the interface cable between devices to you.
Art's devices can communicate with each other as long as the clock frequencies or bulk rate is within
plus or minus 5 percent of each other.
On the other hand two devices communicating with SBA operate from the same clock source.
Typically the master device creates the clock and a slave device uses the clock to latch data in and
send data out.
The SBA typically consists of four wives or four pins.
These are the is the eye the SD or the S C O K and the C in many chips the S D I S D or s C.L. kit and
seeing these signals are alternatively named as the Morsi the ME so the C K and the SS pin.
So if you find Morsi missile SDK SS is the same as SDI SD or SC LG and C.
There is also a popular standard called the three wire SBI and a three wire SBI interface bus.
We have the SC l care and the C and only a single pin for data transfer the SBA for way a bus can become
a three way interface.
When D s t i n d S D or data pins are tied together.
However there are some major differences between the standard SBA a four way which we are using in a
three way device in the data transfer protocol.
So for this reason a device must support three way a protocol internally in order to be used as a three
way device.
Many devices support both the SBA for wire and the three way protocol.
Now let's talk about how the SBA works.
So the SBA consist of two shift registers one for the master and the other one for the slave.
Also there is a clock generator in the master side that generates that clock.
For that to shift registers as we can see over here zero hour to pin off the master shift register is
connected to the serial in pin of the slave shift register by the Morsi line and Morsi stands for master
out slave in and the zero in paying off the master shift register is connected to the zero output of
the slave ship to register by the missal line and missile means master in slave out the master clock
generator provides clock to both master and slave shift registers the clock inputs of the shift registers
can be falling or rising.
Age triggered an SBI to shift registers are 8 bits long.
This means that after 8 clock poses the contents of the to shift registers are interchanged.
When the master wants to send a bite of data it places the byte in the shift its places the bytes in
its shift register and generate a clock policies after eight clock policies debate is transmitted to
the slave shift register when the master wants to receive a base of data the slave side should place
the bait in its shift to register and after 8 clock policies that data will be received by the master
shift register.
We shall see how this works programmatically.
Next let's take a look at the SBI clock polarity as we learned earlier in.
You are the communication the transmitter and the receiver must agree on a clock frequency which we
call the bottom rate.
However in SBI communication both master and slave use the same clock.
But the master and slave must agree on the clock polarity and the phase of the clock with respect to
the data C P or L or C pull over here stands for clock polarity and C P H E or C FA stands for the clock
phase at C ball equals zero the ideal value of the clock is zero while at C poorly course one the ideal
value of the clock is one C5 equal 0 means sample data on the leading or 1st clock urge while CFA equals
1 means sample data on the trailing CFA because 0 means sample data on the lead in or first clock edge
while CFA cause 1 means sample data on the trailing or second clock edge.
Also if the ideal value of the clock is zero the lead in or first clock edge is erasing edge but if
the ideal value of the clock is 1 the lead in first the clock edge is a fall edge.