Hello.
Welcome back.
So let's write to a driver.
I'm gonna start off by putting my directives
just pitch them here like this.
And
it just creates a bit of space on here.
And on the score on the score Main and we start off by
enabling know what GPL you Bill GPL you win it and then what I'm gonna do is um could you post the video
and try to implement the GPL you in its subroutine on your own.
And once you are done you can on post it and we do it together.
Okay.
Now let's see how that is done.
We've done this on multiple occasions.
So this is the name of the subroutine.
I'm gonna start off by
by enabling DRM the clock access to Q You f first would do this and then think I'm gonna do this faster.
Load
as you are one and then we perform all
our zero hours zero then GPL you F E N and then we store our 0 0 1 and then we wait for a while by using
n o p.
Once that is done the direction register we're gonna use GPL U.
Um I'm gonna use the red LCD here so I'm gonna do a load of the line.
This would be
when I do load R 1
GPL you f d I register the
and then load r 0 are 1 and then all
hours you 5 0
Libby red
and then store a zero hour one like this.
So this was said the red pen as output next week and digitally enabled a pin load.
Load one
next we do digital in April by access and the digital enabled register.
And on this score.
Ah.
And then load
our zero hour one and then all our zero hours zero
the only Democrat pin and then we store
our zero hour one.
Then this is done we can return from the subroutine
right.
So next.
Well we have to do is implement the.
They cannot function to initialize the cystic timer.
Okay.
So once we once we enable what you call you would enable our system timer so we branch to be a
stick on us go in it.
So I'm gonna copy this then come here.
So stick in it.
So first what we do is we um what you say about a cystic timeout before we change anything.
It is advisable to disable it so I'm gonna do.
Load our one and then I'm going to so uh select the cystic control register that is where we enable
and disable the.
I'm gonna move zero into our zero
and then I'm gonna put that into the system control register by saying install our 0 are 1 like this.
Right.
Once we've disabled it we going to load the maximum value to devalue into the um the reload register.
D you x 0 0 f f f f so I'm gonna do it.
Load R 1 course and Vic
t reload
and then I'm gonna load r 0 and there's just going to be the constant s one over here.
Put this into our 0 and then I'm gonna do store r zero R 1.
Okay so once that is done we need to clear a cystic current register and to clear this as the car register
we will need to write a new value into that register so we can simply write C with the m gonna do load
R 1 and Vic SD current score R then move
our 0 Number 0 and then store our 0 r 1 right.
So once that is done we can enable our cystic timer to load by 1.
I'm gonna go back to the cystic control register by doing n fake SD c t RL on a score R and then
I'm going to select a clock source as well as enable it all in this block.
Gonna do move our 0.
I'm gonna do with a constant for enabling this one here.
It's like performing an operation twice a C plus then I'm gonna do a clock source
like this once this is done I'm gonna do move r 0
now I've already done move of store
our 0 r 1 and then B x A law okay.
Looks good.
So in the next lesson we going to implement the cystic weight subroutines.
These are what DeLay subroutines will see in the next.