Hello.
Welcome back.
So in this lesson we should talk about the generic architecture behind interface and power flows to
the process or as you may know embedded systems that interact with the the outside world needs some
form of peripheral device.
In a sense the set of peripherals attached to the embedded device determines the uniqueness of the arm
of that device.
All upper floors are memory mapped and this means the programming interface is a set of memory address
registers.
And as we shall see when we begin coding the address of these registers is an offset from a specific
pair for base address.
Our simplified embedded device over here still shows two items we've not talked about.
We've explained the process all we have explained the eight HP and the APB buses.
We've talked about memory.
We've said the green rectangles are just examples of some peripherals that can be connected to the embedded
device.
We are left with the memory controller and the interrupt controller the memory controller simply connects
that different types of memory we talked about to the processor.
For example when the power is turned on the memory controller may be configured in hardware to allow
certain memory devices to be active.
These memory devices allow the initialization code to be executed.
Some memory devices must be set up in software though something like the under D ROM we first have to
set up the memory timings and the refresh rate using software before it can be accessed.
Now about the interrupt controller it is basically it's basically determines which peripheral can access
the process or at specific times.
There are two types of interrupt controllers available in the standard interrupt controller and DRM
defected interrupt controller.
I shall leave the discussions on interrupt controllers for the V for the future lessons when we're talking
about interrupt only.
So this is all there is to it and I shall see you in the next lesson.