Hello.
Welcome back.
In this lesson we should talk about registers.
Registers are just the most fundamental storage area on the chip.
You can put almost anything you want on a register.
Data Values like time of values COUNTER LIST tables and so on and so forth.
Process or solve a number of registers inside a process of call.
And most of these registers are grouped in a unit known as the register bank.
The 70 PMI process has a total of 37 registers and 30 of these registers general purpose registers six
of them are status registers and one is the program counsel register the arms of registers are arranged
in partially over Lapin banks meaning you as the program I see a different register bank for each process
or mode.
Sometimes this creates a bit of confusion but it shouldn't really simply put out at any time.
Fifteen general purpose registers 1 or 2 status registers an AR 15 which is known as the program counter
register visible to you.
Ask the programmer you always programmed these registers using the same name but dependent on which
mode you are in.
You are simply looking at different sets of registers as you can see here.
They use a mode over here you have our issue through our 14 program counter register and a current program
status register C P S R for sure.
This is what the end of the table looks like.
Actually so as you can see there CPS are actually this a smaller version of the tables.
Let's use this one.
If the process are way to suddenly change to the abort mode for whatever reason it would swap or bank
out registers are 13 and are 14 with different r 13 and our 14 registers.
Notice that the largest register swaps occurs when the processor changes to the fast interrupt mode.
This is partly because the processor is trying to do everything very quickly saved a state of the machine
and restore a new state during an interrupt.
It is normally necessary to drop everything the process is doing and begin to work on one task and this
involves even the state of the machine in transition to handling the interrupt very quickly rather than
moving the data from all the registers on the processor to extend or memory.
The machine simply swapped certain registers with new ones to allow the programmer access to fresh registers.
I know this may sound a bit unusual but way to get to the section on exception handling the banked registers.
Those cheated Gray they are available when the processor is in a particular mode.
For example sports mode has banked registers are 13.
I bought an AR 14 I bought and SPDR I bought.
As you can see every process or more would accept the use a mode can change mode by writing directly
to the the mode bit of the CPRS register which we shall examine later or process and modes accept the
system mode have a set of Associated Bank registers that are a subset of the main 16 registers at bank
register maps one to one onto the user mode register.
So if you change the process a mode at bank register from the new mode will replace the existing register.
While most of the registers can be used for any purpose there are a few registers that are normally
used for special purposes.
R 13 is known as the stock pointer register and it hosted the address of the stack in memory and a unique
stack pointer exist for each mode.
We shall examine this incoming lessons our 14 is known as the link register and it is used to hold these
subroutine or exception return address AR 15 hosted the program counter and we shall we shall see the
at the end of this section.
Both the 70 PMI and the Caltex pipeline architectures meaning that while one instruction is being fetched
another is being decoded and yet another is being executed.
The address of the instruction that is being fetched is contained in this AR 15 known as the program
counter register.
You ask the programmer once normally access this register on less than certain specific cases where
let's say you need to jump to a particular memory location or when you want to recover to a different
destination after an interrupt.
We shall experiment with all of these later.
The CPS R is also known as the the current program status register and can be seen as a state of the
system allowing the program to recover from exceptions or branch on the result or an operation it contains
condition flags interrupt flags the current mode and the current state.
Each privileged state has a saved program status register as we can see in the diagram here.
Each privilege mode has its own SPSS.
The supervisor has SPSS R as FEC a poor test S P S R a port on defined whose spirits are undefined etc.
The SPSS R is used to save the value of the CPS R when an exceptional case since use a mode and system
mode are not entered on any exception.
They do not have an espresso and a register to preserve CPS are is not required for these modes.
Actually in the use of motor system would if you attempt to read DSP SPSS you will get on an unpredictable
value back meaning the data cannot be used.
And if you attempt to write to the SPSS register in one of these most that data will be ignored.
These four bits at the top here are collectively known as the condition code flags and the 8 bits at
the bottom also a condition could fly can be altered by the arithmetic and logical instructions such
as subtraction addition logical shift etc..
We shall examine the meaning and relevance of these in our code.
The F and a bit here.
The interrupt to disable bits which disable the fast interrupt in the normal interrupt.
If the asset the TBD is known as the status bit and it is used to indicate the state of the system so
you ask the programmer will only read this bit not right to it as we shall see later.
There is a different requirement associated with this bit when it comes to the cortex and architecture.
If the bit is set to one it means the core is executed and in thump mode.
The list significant bits are used to set the.
The mode of the processor.
When bit 4 through 0 are set at 1 serious serious serious 0.
Then the process is set to operate and use a mode in the same way.
When these bits set at 1 0 0 0 1.
Then the process operate and fast interrupt mode and in the same way when all four data set when 0 5
bits remember its bid for 3 0.
So when all 5 bits are set at 1 1 1 1 1 then the system is operating in the system mode.
So this all there is to it and I'll see you in the next lesson.