Hello fellas.
Welcome back.
In the previous section we talked about embedded systems used in the process or in this lesson we shall
look at how data moves between different parts of the process of core.
You had a program I can think of the ARM core as a functional unit connected by data process where the
arrows represent the flow of data.
The lines here represent the boxes and the boxes represent either an operation unit or a storage area.
From this diagram we can see not only data but also the abstract components that make up the ARM core
data enters the core through the data bus the data bus may be on instruction to execute or add data
item.
This arrangement here shows a Von Neumann implementation of the arm process or as we can see data and
instructions share the same bus destruction decoder translate instruction before they're executed it's
instruction executed belongs to a particular instruction set since process source use risk architecture
and a feature of risk.
Architecture is the lodestar architecture.
This means it has two instruction types for transferring data in and out of the process so load instructions
copy data from memory to registers and store instruction copy data from registers to memory.
There are no data processing instructions that directly manipulate data in memory meaning data is solely
processed in the registers data items are placed in the register file and as we mentioned the registers
are like 32 bit fast accessible storage as soon as the Army Corps is 32 bit process so most instructions
treats the registers as hold in a signed or unsigned 32 bits value design.
Extend hardware over here convert age between 16 bits numbers to 32 bits numbers as they are read from
memory and placed in a register.
Instructions typically have 2 source registers are in an hour and a single result or destination register
our deep source operations are read from the register file using these internal buses a and b the arithmetic
logic unit known as a queue for short or the multiply accumulates unit known as the Mac takes their
register values R and R M from 8 and b buses and compute a resource to data processing instructions
right resort in R D directly to the register file load and store instructions use the ACLU to generate
an address to be held in the address register and broadcast on the address box.
One other important feature of the process or is that register R and can alternatively be processed
in the Barrow shift before it enters the ACLU together.
The Barrow shifter and the ACLU can calculate a wide range of expressions and addresses after passing
through the functional unit.
The result in R D is written back to the register file using the resort bus for load and store instructions.
The incremental updates the address register before the call reads or writes the next register value
from or to the next sequential memory location.
The process of continuous execute and instructions until an exception or an interrupt.
Changes the normal execution flow.
So this is all there is to it.
Remember to leave your questions below or send me a message and I shall see you in the next lesson.