Hello fellas.
Welcome back.
In this lesson we're going to talk about the concept of pipelines.
Basically a pipeline is the mechanism a risk process or users to execute instructions using a pipeline
massively speeds up execution by fetching the next instruction while other instructions are being decoded
and executed.
One way to view a pipeline is to think of it as an automobile assembly line with each stage carrying
out a particular task to manufacture the vehicle defect lows and instruction for memory the decode identifies
the instruction to be executed and the execute processes the instruction and write the results back
to register.
This is a very simple pipeline.
It is a three stage pipeline similar to the one used in Codex M and seven process source.
Here is a sequence of three instructions being fetched decoded and executed by the process or it construction
takes a single cycle to complete.
After the pipeline is filled as we can see the three instructions are placed in the pipeline sequentially
in the first cycle.
The process or fetches the art instruction from memory in the second cycle.
The process of fetches the swap instruction and decodes the art instruction in the third cycle.
Both this up and add instruction are moved along the pipeline to add instruction is executed to sop
instruction is decoded and they compare or see MP instruction is fetched.
This procedure is called Fill in the pipeline.
The pipeline in effect allows the corps to execute on instruction every cycle.
As I mentioned this is a simple three stage pipeline architecture.
Some implementations of the pipeline architecture are used in some cores like the cortex a family used
in devices like the iPhone and other smartphones have as many as 15 stages as the pipeline length increases
the amount of work done at each stage is reduced which allows the process or to attain higher operating
frequencies.
This in turn increases the young the performance and the system latency also increases because it takes
more cycles to fill the pipeline before the call can execute on instruction.
The increased pipeline length also means there can be data dependency between certain stages and we
can write code to reduce this dependence using instruction scheduling which we shall explore in future
sections.
The pipeline has not processed on instruction until its past is complete the through the execute stage
in the execute stage the program counter register always points to the address of the instruction being
executed plus 8 byte and this corresponds to the fetch stage of the pipeline.
In other words the piece always points to the address of the instruction being executed plus two instructions
ahead.
There are three other characteristics of the pipeline worth mentioning.
First the execution of the branch instruction or directly modifying the course is the Army Corps flush
its pipeline.
Also some arm architectures like the arm 10 uses the branch predictor which reduces the effect of pipeline
flush by predicting possible branches and loading the new branch address before the execution of the
instruction.
Finally the instruction in the execute stage will complete even though an interrupt has been raised.
Other instruction is in the pipeline will be abundant and the process will start fill in the pipeline
from the appropriate entry and defect a table.
So this all there is to its fellows and I shall see you in the next lesson.