So in this first video, what will be understanding its will be completing an entire floor walk right
from creating a project till downloading a project onto an FPGA.
OK, so this will give us an idea of fundamental idea of an entire floor will not be discussing any
step in a greater detail right now.
Our agenda will just be to go through a process because as we progress will be finding, we are building
up our experience and agree to deteriorate.
In fact, in next June, you will be understanding some of the options why we are doing that.
But for this specific, we will be focusing majorly on the process, right?
So we already started to provide this could be done by just double clicking on the like, and that has
been added by default.
OK, when you complete an installation.
So here I am utilizing the vital two thousand eighteen point three, right?
We start with the Create project.
This is the first step that we do know whenever we start creating a new project.
Here you do see two more option open projects, so this will be utilized when you already have an existing
project being created.
All of you are doing, you want to open a door.
And if you want to look for the example project provided by default with an IED, you could just glue
for the open example project.
Great.
We click next.
Then we get an option to select a directorate, right?
So once you select the directory, there are multiple folders will be created required for performing
a different process.
All finished speaking.
Right.
So here I have chosen the project name, which is by default, Project White and then the location where
I'll be storing a project right click next.
Now here you see a fire option by default will be choosing an ideal project.
Later on, we'll be discussing what each of an option will do for it.
But here we will proceed with an actual project, and in most of the time, we will be proceeding with
the Nortel project right next.
So here, the target language that we'll be using is very low simulator languages mixed, and we won't
be creating any file because we will be predominantly working on and we will do IP integrator.
So dare we design our block?
And then we will be generating in code out of the crate so we do not need to specify any SD.
So once we complete our IP related work, OK, and we start building our own IP to interface with anything
there, we could add a create file, but at least for a few sections, will not be doing it right click
next.
Considine will be understanding later on what situations we need to add a constraint, but when we consider
it an IP which recognizes our there, we do not need to add a constraint, right?
So here we will be.
Skip this process of adding if constraint, you need to select the correct that is the mandatory step,
because word file plays a very important role in recognizing your preference when you add an IP, right?
So the word that I have with me is saying take two seven one zero, so I'll just be selecting that word
and then proceeding ahead, right?
So this is the word that I have with me.
You could select any other see if you have, as I would say, seven to zero or Zabel.
You could select your respective work, click next and then hit finish.
No, this will add the necessary folders, which are required at a different.
Steps when we perform an FPGA right now, you are inside and we board wildly, so you see a small step
where you'd be finding all the sources are OK and then flew.
So this plays a very crucial role.
We'll be discussing each and every step as we progress right now.
We start with creating a blog designed, so the second option that you have is create a blog detailing
the first option.
Allow us to hide of a lot of your total order system relaxers.
But since we are not writing it right now, we'll be proceeding to a next option.
OK, which is an IP integrator, so we'll take on create blog design.
We'll stick to our deployed name, which is design one, and then we'll proceed.
So here we have a block design, you click on this plus button or this splatter pattern to add an IP
rate to the processing system for us who will be using.
So it will just be searching for letting processing system and double clicking on it will add the zinc
IP onto a canvas, right?
Once you add the zinc IP, the next step is to perform a block or permission.
Know what block automation do will be.
Understanding later on will just be clicking on block automation.
We'll be keeping our default option, which are checked by default.
So you have a processing system which just check a pliable preset, which is also checked, and then
we will be clicking on for this first video.
We will be working around Gaudin.
You are right.
So along with the you what you could see, there are various peripheral which are enabled by default.
So we require that each year there will not be disabling it.
But fixed style.
We only require to work on a new lock, right?
So if you just double click to reconfigure an IP?
OK, so here the easiest way is to just look for a block design.
So all the peripherals which are having a checkmark, I've been enabled by default when we are pliable
preset, right?
So you what is Enable GPI is Enable SD card is Enable USB is Enable.
Ethernet is enabled by default and space also enabled by default, right?
So you could just go ahead and double click on any of the block which you want to disable.
So I'll just be double clicking on GPI.
OK, and this will take you directly to the specific tab, which allows us to disable our different
option, right?
So we do not want tonight.
We do not want the USB SD, we want you out because we will be working around with it, and then we'll
also be disabling the rest of the basic right.
So this is the first step where we just enable and you are right, this is the first step that will
be doing.
The next thing is, if you just go to a peripheral view, OK, you have a card s.p.a.
So we do not want to use it will again be disabling it.
Now, when we consider B is truepill configuration, so we have our IP that will be interface with that
X8 interface, right?
So all APL, we have an IP and then all piece, we are required to have any kind of issue in a PSP configuration.
You will be finding all the default option that allows us to interface the APL APIs OK to the processing
system and by default, if you just analyser block data.
So we do have one of the eixa interface, which is enabled by default that is makes AGP zero, but we
are not targeting any IP over here, so we'll just be disabling it.
If you just go to IXI non-secure enablement, OK, and then here we have a cheap master A.S. So we'll
just be I'm checking it, then we haven't been able, Slovic say, even in high performance leveque
weeks.
So this will be by default check rate peripherals.
We already selected a new OK.
OK.
The next thing is a clock configuration, because you do see that we have one off the clock port, which
could be utilizing and plb is been added.
But since we are not adding any IP, we'll just go to a clock configuration and then you have a pale
fabric clock, so you just uncheck it, right?
So those are some of the options that we need to disable.
And then we click, OK.
OK.
So once you do this, you'll be fine.
If we are left with a limited number of peripherals and as well as few ports are been by default remote
which have been added, then we both on mobile automation, right?
The next thing is to clean up a diagram.
So to do that, we have a region regenerate out over here, right?
Will just be clicking on it so it will clean up our diagram.
And then once we complete our block design, the next step is to verify whether all the mandatory connections
are made to their respective work, right?
So to do that, to perform a verification, we just need to click on validate design.
So once validation is successful, once you get this message, the validation successful and there are
no more headers or a critical warning in the design, you could proceed with a generation of and still
code, right?
Remember an entire flow that you are seeing on and through navigate to work on and.
So we could not directly use of log design.
So first, we need to convert the block design to NHL code and then only we could proceed with the steps.
We go to a small step.
So we go to a small step.
Right click on the blog to say this is our block design and then create an HDL wrapper.
So this will change and still cool for us, which will be utilizing to complete the rest of the process.
One good part about we.
Is when you do not had a user specific IP, so we automatically create a constraint for us, for example,
here.
We created a block automation and then we able to see this very right, so we haven't added anything
which.
Seeing do not understand yet, or we do not understand yet.
OK, so we do not need to add a constraint because once a block automation create opportunity for us
by default, it also recognised and rate of to where we need to connect dispute.
Right.
So whenever?
Vital recognize the ports that has been created by default, we do not need to specify a constant rate,
and that is an advantage, as we will be discussing more on this as we build this.
But here we have not added any user specific IP or user defined IP yet, which is not recognized by
the light.
So we do not need to add a constraint.
Remember this fact into me?
OK.
And then once you are still called Israeli now we are ready to perform all the process, right?
And since we are not working on adding a constraint because constraints are already added by default,
we could just proceed with the addition of a bitstream.
So this will automatically perform synthesis implementation, then generation of a bitstream which could
be utilized to.
Downloading hardware image on an FPGA.