You are saying is the next step is to perform a validation of this and to what validation of design
do is it would check whether all the mandatory collection required for all the peripherals are met or
not.
Right.
So we'll just be clicking on validation of our design excellence.
Validation is successful.
OK, so we could proceed for generation of us.
So here we have our bureaucracy.
We go to a small step over here and you could see we have our doctors and we're here.
So just right click on the blog U.S. and select Create Right and then you get two options.
But we will allow be wide open indeed the wrapper for us.
So just keep the default option and hit on the right.
So once Soul School is ready right now, you could see the Flow Navigator light, so flow.
Navigate it, highlight the different steps that we perform in an FPGA design for right.
So we perform a simulation analysis and synthesis implementation and finally reach an Databricks room,
followed by programming and FPGA.
Right now, you will see we have a two intermediate step, so synthesis is one of an intermediate step
and then generation of objects.
OK.
So when you perform synthesis this assume that you have your two points which are present, right?
So we have a DDA and Fixé, which is present in our design right now.
If your design consists of a food which are not connected to any given week, then you need to perform
the synthesis first before proceeding to generation or else if you are, all the polls which are presenting
their design are all really connected to the respective FPGA.
And then you could just go ahead and start generation of qubits virtual.
All the intermediate steps will be automatically performed and then assuming we can do so, next question
is how you know that all the pools which are present in the design are connected to the respective pins?
Right.
So we have two methods to do that.
So the simplest method that we have with us to exactly know whether all the pins which are present in
our design are connected to the respective then or not.
You just go in and then perform run synthesis, right?
So this will open up a new planning view where we will be getting the list of use which are present
in our design and whether they are connected to any PGA pin or Rachel.
So as we progress, we will also be understanding one more method that we have to quickly know that
all the pools are connected to their respective right.
So if you utilize any of this pool in your design right, so it will automatically have this yellow
checkmark neighboring to its name, right?
So will be understanding since we are not utilizing any of this will benefit you right now.
So you won't be finding any check mark over here.
Right.
So we will just be waiting for synthesis to complete and analyze I planning where we will even to find
out whether this two pools that are gotten fixed value is connected to their respective right.
So I think this is we will be selecting opens and this is design and will click OK, right now here
you could see by default, we have a device and package you and at the bottom you see and I save.
So I design consist of I fixed, right?
And you could see that these are already being connected to the respect respective have because you
could see to check Mark over here.
And if you just click on this arrow, you could actually observe the events which are there for that,
right?
So this basically suggests that all the benefit.
OK, so here you could see the you, which is also connected to their respective pins.
So whenever you open up an outlining view and as soon as you see checkmark on a fixed tab, we'll get
that basically mean the boot has been connected to the respective FPGA hardware.