1
00:00:00,060 --> 00:00:05,450
The latest consider this situation where we have a zinc processing system and have previously added

2
00:00:05,450 --> 00:00:11,950
any excitability, and we have configured it to operate at single channel rate, so we have changed

3
00:00:12,060 --> 00:00:12,660
a bit steam.

4
00:00:12,690 --> 00:00:17,090
We also have verified an application in and write this idea, right?

5
00:00:17,120 --> 00:00:24,330
So now our regulators to modify IP, that is instead of a single general label, we want to utilize

6
00:00:24,330 --> 00:00:25,290
a dual channel, right?

7
00:00:25,290 --> 00:00:30,330
So we double click on in the Excite UPI IP to reconfigure it right.

8
00:00:30,630 --> 00:00:38,700
And now we choose to use the slice, which is that we have on the go and configured our second child

9
00:00:38,700 --> 00:00:39,720
to work with it, right?

10
00:00:39,720 --> 00:00:46,380
So second, we will be performing an action automation, so this will automatically connect this boot

11
00:00:46,500 --> 00:00:49,500
to the respective switch that we have right now.

12
00:00:49,770 --> 00:00:54,030
Remember, in the previous case, we have a single channel and with an updated.

13
00:00:55,070 --> 00:01:02,300
Block design, we have to change with this now we proceed to first trendy and still dapper, right?

14
00:01:02,330 --> 00:01:09,050
So with this updated block design now we have created the fresh instance of is still dapper, right?

15
00:01:09,890 --> 00:01:17,090
And once rapid generation is successful, we go ahead and proceed for generation of this new hardware

16
00:01:17,090 --> 00:01:17,390
design.

17
00:01:17,450 --> 00:01:17,780
Right?

18
00:01:18,660 --> 00:01:22,680
So we proceed with the generation of Bitstream for this new hardware design.

19
00:01:23,690 --> 00:01:30,860
Now will wait till the extreme generation is successful, and then we'll try to update this specification.

20
00:01:30,980 --> 00:01:32,180
OK, and then why you decide?