So system generator also rich on some implementation of Digital Signal Processing libraries
and some DSP functions there.
So we can process our audio/video or multimedia with those digital signal processing library
and we can even utilized this DSP functions; for DSP block for like communication and other projects and we can
automatically generate the hardware description language that is VHDL/Verilog from that System Generator
-Sys. Gen.
And this system generator is available at Simulink ontalking about MATLAB/Simulink, so we can go
to the traditional Simulink Design and design our projects but we need to have some opening;
We need to open Systems Generator interface from our FPGA design tool installation.
So if you go to the program list on the Start menu of Xilinx and there is a icon called Systems Generator. So
Systems Generator is the interface between traditional FPGA design tool and Simulink so we can so utilize some verified blocks (model)
or blocks of Simulink for Systems Generator and later on we can include Systems Generator icon in the design and we can generate
HDL and we can implement that Systems Generator project directly to the hardware that is FPGA and we can simulate that design which
we are going to talk in another presentations/slides.
So as we talk recently;
So if you want to configure your Systems Generator which we also talk in,
previous section;
But we will /let's resume it and you can go to these type of icons.
Actually we are talking about Windows 7 environment operating systems, so you can; you can go to a Systems Generator
MATLAB configuration inside that Xilinx installation on Start Menu and you can go to
configure the Systems Generator which we have already talked on previous section and you can open that Systems Generator
from this icon; that is second icon; that is Systems Generator.
So if you click this Systems Generator then it would automatically open the MATLAB for Systems Generator
interface.
So here we have VIVADO environment in Windows and ISE environment; ISE Design Tool environment
in Windows. So, both have similar type interface for Systems Generator and so we can configure our Systems Generator
from VIVADO Design Tool or
ISE ; from any of this one. So, and on talking about System Generator based design flow actually on each design
flow, we can; we need to insert these type of icon in our design block design so we can design
our block/model; or we can have block design in the System Generator and we can generate as HDL from that Block/Model.
So System Generator provides us interface provides us facility or features for generating the
HDL-Hardware Description Language.
And we can synthesize that HDL implemented it and upload it to the FPGA in traditional manner or we can even
directly go to System Verification, so we can run our generated HDL directly into Hardware from that System Generator
Option. And we can simulate the; or Run the co-simulation from that System Generator and we can even do the
Functional Simulation, timing simulation.Actually the yellow part is based upon System Generator and other
white part is based on traditional FPGA design tool that is ISE or VIVADO.
So we can export out HDL to ISE/VIVADO and synthesize it implement it and download on hardware/FPGA. Or we can
directly goto system verification, from that System Generator it automatically allow us to the System Verification Option.
And another design flow is,
We can even do the functional simulation from that System Generator.
And other white parts on the figure are for traditional FPGA Design Tool.
We can see; we can create our black blocks in Simulink or System Generator interface that we can create our block building
block as other blocks in System Generator and we can also include these type of ModelSim block for that
we need to install some ModelSim for System Generator and we can do the hardware Co-simulation like we can see here.
And if you want to implement on hardware then there would be two options; one we can do that to process from System Generator,
or we can export our HDL from System Generator to traditional FPGA Design Tool (Xilinx ISE/VIVADO).
And Second flow is again here,
So we can go to HDL generator we can Synthesize the design and it can completely be drawn from System Generator
option or we can export that HDL to Traditional FPGA Design tool- ISE/VIVADO design which we are talking on.
So for creating System Generator based design.
So what we can do it we can open our System Generator from the Start Menu of your Operating System inside the
start menu and inside it
there will have some ISE/VIVADO program list and you can go to System Generator and open the System Generator
and if you click on System Generator it will open the this type of options or menu then you can create a new block design
option and
you can just select block of System Generator and import that block on your current design so you can
customize it and you can integrate it with all other building blocks from the block design option on
System Generator and you can select and search different types of block there.
and first time if you are configuring your System Generator then it will take
little bit more time for synchronizing all the building blocks for System Generator from Simulink & ISE.And, after you did the
project first time then in the next times or in the next projects it will do much faster
on Searching and importing those block from ISE & System Generator library and we can see there like basic elements as Counter,
and delays like block are there and for communication
There are some error correction block and M code block and black blocks are in control logic. We can see FFT & FIR
and FDA tool.Actually , we are going to utilize this DSP building block on System Generator later.So, there are
FDA tool FFT & FIR building blocks which we are going to utilize on upcoming projects and there
are different xilinx blocks in index and mathematical blocks, accumulate blocks in math, like math section. In memory
there is a dual port RAM, Single Port RAM. In tools there is Resource Estimator,ModelSim,WaveScope etc.
and on talking about this all Xilinx blocks inside that all Xilinx Blocks there is block called System Generator (icon).
So we need to have that System Generator Icon on
Every project which are targeted to implement an FPGA. so for talking about Configuration of each block, so here we have
examples of
FIR compiler 5.0 , this is Xilinx FIR compiler blocks so we can customize this block as our requirements.
so we need to just double click on this type of Block/IP.
So if we don't click on this IP then what happens is, we can see the type of option there, so we can configure our
variables there. so we can see Arithmetic type and it takes Unsigned or 2's compliment of values in arithmetic
type and we can go too or we can customize implement with Xilinx Smart IP Core, actually these are the
general customization options which will not available in each block
But most of the block have this type of options.
So, we can set up latency, we can set up some overflow and quantisation, we can override with doubles,
we can have and we can set a precision and some sample period for like FFT and IFFT or FIR and IIR Filter
block. So,we can set up the parameters and here we have Number Format in System Generator actually FPGA are
good for Fixed Point Computations. so if we want to process some Floating point data then we
can Offload or
we can process those data on processor and if we want the process Floating Point data with FPGA?
Then we need to convert it into Fixed Point format or it will automatically utilize Fixed Point library.
So here we have some Fixed Point representation so we can see Xilinx Blockset's uses n bit Fixed Point numbers.
so that Fixed Point number is 2's complement of or two's complement is optional there.
So it's actully obtain the Fixed Point value from the floating point so it converts automatically into fixpoint
Signed o Un-signed.
So we're going to talk about this "Number System" in
upcoming lab also and we're going to go to "Gateway in out block" so that block is available at Xilinx Blockset's,
MATLAB I/O and Gateway In/Out.
So this block actually used for that Floating Point to Fixed Point Conversion, Fixed Point precision so we can provide normal output
to this Gateway In/Out block and it will convert that normal input to Fixed Point Precision data.
So, we can setup the sample period for some time of or for some type of like processing block
like FIR , IIR block.
So, we need to setup our some frequency; some sample period for processing audio and
multimedia and we can set up sample period as 44100. So, that means it will be executed every 44100
times per second so we can also remember the Nyquist theorem. So, it shows that
Sampling frequency must be 2 times of Maximum frequency.
So this is taken at sampling frequency,
That is 44100.
That is one by 44100 is that is the period of; one of the block functions operation per second.
This is the System Generator token so this System Generator token is actually needed for
each and every System Generator block design.
So if we don't include this then that (HDL generation/Co-Simulation) will not work for us.
So this icon only provides us some options for FPGA design, offloading FPGA or targeting FPGA design
options from here.
So we can even convert HDL from our System Generator block design, Block Design into HDL
from this icon.
So this provides some HDL netlist generation option and Bitstream generation option and run
Co-stimulation option
So this block is heavily important for us.
So inside that if we double click on that block, we can see this type of options or this type of functions there.
so we can check the Compilation as Netlist and we can select the part and we can select the Synthesize tool
And we can select the Hardware description language which are going to Output, targeted directory, project type etc.
And we can see here the clocking features here so we can set up the clock, FPGA clock & location
also.
Until this System Generator actually we just have talked about MATLAB/Simulink & System Generator.
So, MATLAB/Simulink provides System Generator interface for Xilinx ISE or VIVADO.
So let's talk a little bit about Xilinx ISE & VIVADO. So, ISE design suit
can import that System Generator exported design,
That HDL design and utilized that design for synthesizing ,implementing and generating it can again
program the FPGA.
And ISE Design Suit,
We already know about this tool/things actually provide a System Generator interface for us.
System Generator also provide some interface/ basic graphical user interface of ISE design suit. On talking about
Xilinx FPGA programming with HDL Coder, actually HDL Coder is another part so it actually provides us some functions
,some functions means we can convert our design into HDL format by directly using HDL coder compiler.
It also can convert normal MATLAB projects into HDL format and so we can
utilize that HDL in ISE or in VIVADO Design Suit and
used that HDL for traditional design flow that is synthesizing, implementing
and generating Bitstream.
So this HDL coder is important for conversion of MATLAB algorithms and even Simulink models
into HDL format and actually System Generator also provide some extra features like generating Bitstream implementing hardware
Co-Simulation.
And HDL coder can only do that is conversion of HDL from that MATLAB algorith and simulink Model's. So,
HDL coder is just a converter and System Generator is actually not only the converter, System Generator also provide
some implementation, Co-simulation and like Bitstream generation option there. So, here we can see generation
of HDL source code.
So after we implement the MATLAB algorithms so we can utilize that HDL coder and convert that MATLAB algorithm into
RTL(Register Transfer Language) or HDL format.
And we can talk about "Program Xilinx FPGA using HDL Coder with Xilinx System Generator" so we already talk about
System Generator. Actually, System Generator provide us generation of Hardware description anguage based netlist
implementing directly on FPGA, running co-simulation & generating the project like options/features and we have
"Program Xilinx Zynq SoC devices with Embedded Coder & HDL coder". Actually there is also program called embedded coder
that is necessary for programming that processing system in Zynq FPGA.
So Zynq FPGA can be programmed by HDL coder for programmable logic (PL) & embedded coder for
processing system(PS). So, this features will also talk on a later session.
So we have some basic explanation of all these features actually Zynq uses; Zynq 7000 is the 7 series of FPGA from Xilinx.
so it uses AXI interface for communication between traditional programmable logic and ARM
processor inside that Zynq 7000.
So we need to program FPGA that is programmablel logic with the HDL coder based designs and embedded coder
based
design need to uploading into ARM processing core that is processing system core.
So we need to know about two things.
So we already talk: HDL coder is necessary for Programmable Logic, while both
HDL & Embedded coder are necessary for Zynq based design.
So HDL coder is really good for traditional FPGA design.
While,
If you want to or if you want program Microblaze or Processing system or ARM processor inside that FPGA then
we need to have in that Embedded Coder. So, we can see the design flow here so embedded coder targeted for ARM
processor inside that Xilinx Zynq.
and HDL coder is targeted for FPGA core that is Programmable Logic inside that Zynq.
So we can Run our project.
So both things are integrated inside that template and it'll be uploaded to FPGA from that
MATLAB/Simulink interface.
So another thing we have talked about HDL verifier actually HDL verifier provides some design and
verification option's so we can simulate our design and we can run our FPGA design in
Hardware in Loop option so we can verify our design and we can also integrate some Modelsim/Cadence
and QuastaSim simulator inside that MATLAB/Simulink .so that HDL verifier allows us to create testbench and run the simulation.
So HDL verifier design flow can be seen here,
so MATLAB/Simulink is there
And we can design on MATLAB/Simulink based project that is MATLAB based algorithms and Simulink based
model designs and we can use HDL Verifier for Co-Simulation and FPGA in loop.
So if we use FPGA in loop then it will go to FPGA and it will again provide feedback to HDL verifer i.e MATLAB based
interface.
And if we run the Co-Simulation then it also again run the simulator and updates the result in HDL verifier.
So here are some references, actually there are some user guides like UG897 which is VIVADO system generator user guide.
and there are some references for MATLAB that is mathworks.com
and xilinx.com
So you can review those links.
So guys we would have Lab session in an upcoming video lecture so we'll continue on in another video.
Thank You Guys!