Hello and welcome to this course: Digital System Design with High-Level Synthesis for FPGA: Combinational 1
Circuits 2
Are you familiar with C/C++ language and would like to work with FPGAs straightaway without 3
spending months and months learning complex hardware description languages? Then welcome to this course. 4
Are you a software or hardware student who is going to learn the latest technologies about FPGA without spending 5
too much to learn low-level tedious logic optimisation techniques? Then welcome to this course. 6
Are you a researcher with software or hardware background who is going to take his or her research to 7
the next level by accelerating algorithms with FPGAs? Then welcome to this course. 8
I am Mohammad. 9
I have a PhD in Electronics and Computer Engineering. 10
I have been teaching electronics and programming courses in several universities for more than 10 years. 11
I have been doing research on reconfigurable computing for more than 20 years in different universities. 12
I am the author of several conference, journal and transaction papers, published by IEE/IEEE . 13
and ACM 14
Also, I have developed several real applications on FPGAs during my research career. 15
I’ll be your instructor and guide in this course. 16
My first goal is to simplify the new technologies in reconfigurable computing to be used by students 17
and researchers who have no or little background knowledge of FPGA. 18
You may have heard that FPGA design is complicated, 19
yes, it is, if you follow the traditional HDL design flow. However, high-level synthesis design flow 20
makes the FPGA design easy and accessible for a large group of software and hardware engineers. It 21
is my mission here to uncover the high-level synthesis design secrets with a straightforward and exciting 22
approach. 23
We are going to learn, discover and explore the topic of high-level synthesis, HLS. 24
HLS is an entirely new hardware design technology. 25
It is a set of hardware design-flow, optimisation techniques, coding styles, software tools, and debugging 26
mechanisms. 27
HLS is a technology that uses a high-level language such as C/C++ to hide all the traditional hardware 28
design complexities from designers. 29
So, if you are curious about high-level synthesis and don’t know where to start, 30
Welcome to this course. 31
If you are a university or college instructor, lecturer, or professor who wants to add an HLS flavour 32
to the traditional HDL hardware design flow, then welcome to this course. 33
If you want to show that you are clever enough to work with FPGA like a pro just in a couple of days, 34
then welcome to this course. 35
This course is based on the Xilinx HLS technology, 36
including software toolsets and FPGA-based hardware platforms. 37
The technology is well presented, and there are several examples, designs, applications, and supports around 38
it. 39
presented in this course and provided by Xilinx or the HLS community. 40
The technology is already used by several companies to design many commercial devices, including NVIDIA 41
was able to simplify their code by 5X using HLS  HLS decreased design time by 50 per cent 42
and overall development time, including verification, by 40 per cent. 43
Google Develops WebM Video Decompression Hardware IP Using Technology Independent Sources and High 44
-Level Synthesis 45
This is a list of other companies that are using HLS in the design flows. 46
In this course, I will use the Basys3 entry-level FPGA board to demonstrate several HLS design 47
techniques. 48
The Xilinx Vivado-HLx software toolset is used to develop logic designs starting from C/C++ code 49
down to the FPGA 50
bitstream 51
If you have a budget of a few hundred pounds and are going to learn very advanced topics on HLS and FPGA, 52
then welcome to this course. 53
You only need to spend a couple of hundred pounds to purchase the Xilinx Basys 3 FPGA board, and 54
all the software tools are available for free via the Xilinx website. 55
This course is the first of its kind that builds the HLS design flow and skills along with the digital logic 56
hardware circuit concepts from scratch. 57
This course is the first of a series on HLS in designing hardware modules and accelerating algorithms 58
on a target FPGA. Whereas this course focuses on combinational circuits, the other courses in the 59
series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, 60
and hybrid CPU plus FPGA heterogeneous systems.