Iteration statements or loops in a software language repeat a group of statements a certain number 1
of times, or while a condition is fulfilled. 2
These statements make the programming much more manageable and reduce the program code size. 3
Using iteration statements are also very useful in hardware design. 4
In this section, I will explain how to use parallel iteration statements in coding combinational hardware 5
designs. 6
Iteration statemen ts are part of the control flow in a software program. They help tasks execute several 7
times, sequentially on a different data set. 8
These statements are introduced by the keywords 9
while, do, and for. 10
Repetitive patterns can be seen in many hardware designs in which the same task should be applied to 11
a set of data, for example to all the bits in an n-bit data. 12
However, there are differences between the execution of a software loop and a hardware loop. 13
The main difference is the parallelism execution in the combinational hardware circuits that is modelled 14
by dataflow, in contrast to the concept of sequential execution in software programs that is modelled 15
by control flow techniques. 16
This section focuses on the techniques to use loop statements in describing combinational hardware circuits. 17
This section consists of 10 lectures. This lecture introduces the section. The next lecture 18
gives you a big picture of a repetitive hardware structure to be used later throughout this section. Lecture 19
three explains using a for-loop statement to describe a repetitive combinational pattern in HLS. The section 20
also introduces the loop unrolling optimisation technique. 21
The loop unrolling technique cannot be applied to all loop statements in a code. Lecture four explains 22
a specific coding style for a loop to be synthesised into a combinational circuit. 23
To demonstrate the combinational loop coding style, Lecture five will introduce the parity-bit generator 24
design example. 25
Then Lecture six will explain its implementation in HLS. 26
An optimisation technique to reduce the propagation delay of the parity generator digital circuit is 27
explained in the seventh lecture. 28
Describing the optimised parity-bit generator in HLS would be the topic of the eighth lecture. Lecture nine implements 29
the optimised design in the Vivado-HLS. 30
Finally, the last lecture will give you a couple of exercises to practise 31
all the concepts have been explained throughout this section.