The loop unrolling technique cannot be applied to all loop statements in a code. A specific coding 1
style is required to be able to fully unroll a loop and synthesis it into a combinational circuit. 2
In this lecture, I will explain some of the related coding styles. 3
When we add the unroll pragma to a loop statement, the synthesis tool unrolls the code at compile time 4
so it should know the exact number of loop iterations. 5
In other words, only loops with static bounds, which are fixed and know at compile time, can be 6
fully unrolled by the HLS tool. 7
The number of loop iterations can be defined through a macro such as this code in which N is defined 8
by a define macro. 9
Alternatively, a const variable can be used, as shown in this code example. 10
However, the for-loop in the third code cannot be unrolled as the number of loop iterations depends 11
on n which is a function input argument and is unknown at compile time. 12
Notice that in this case HLS tool gives a warning message and keeps the loop rolled and generates 13
a sequential circuit instead of a combinational one. 14
Fully unrolling a loop structure results in a separate hardware circuit for each iteration. 15
Therefore, there should be enough hardware resources on the target FPGA to realise all the instances; 16
otherwise, the logic synthesis phase will issue an error. 17
The Xilinx Vivado-HLS unrolls the loop and performs the high-level synthesis regardless of the 18
available hardware resources and only gives warning messages in its report. 19
However, if we don’t pay attention to the warnings, the Xilinx vivado logic synthesis tool later along 20
the design flow will complain about the lack of enough resources and won’t generate the FPGA bitstream. 21
As an example, consider that our target FPGA has 20800 LUTs. 22
Let’s assume that one instance of the task function in this loop requires 100 LUTS. 23
If N=10, after synthesising this code about 1000 LUTs are required. As it is less than 24
20800, the for-loop can be implemented later. 25
However, if N=1000, then 100000 LUts are required. As it is greater than 20800, 26
20800, 27
it cannot fit in the target FPGA. 28
In the next lecture, I will take a real example to explain how to use the unrolling techniques in practice. 29
The takeaway message from this lecture is: To fully unroll a loop in HLS, The loop bounds must be known at 30
compile time. And there should be enough resources on FPGA, e.g., enough LUTs 31
Now the quiz question. Which code can be synthesised into a combinational circuit?