Let's design a digital circuit for the party we generate, let's consider to be data and its associated
party.
With this truth table shows the value of the event and operative its.
That's can be seen, the parity is the inverse of the event.
Also, an extra gate implements the even part of it.
Therefore the following, the logical expression generates a parity bit for two bits, D1 and D2.
INSEE, we can use bitwise Exaro operator to show this expression.
Now, if you assume attribute data, then the circuit depicts the particle generator for the three bit
data.
Generalizing the idea of parity with generating using X or to convert a wide bit data is a straightforward
each extra input adds an X or gate to the chain.
Therefore, the parity bid for a binary value with W bits can be generated by a chain of at least minus
one X or gaits.
If there is one one zero zero one one zero zero, then the even part of it is zero.
Let's have a look at the circuit propagation delay, if we consider that the propagation delay of an
X or gate is Delta, then the propagation delay of the whole design is at least W minus one delta.
Now, the question is, how can we reduce the circuit propagation delay to improve its performance,
the next lecture will answer this question.
This is our takeaway message, the chain of ex or gates can generate the parity bit for a binary data.
Now, the quiz question, the following figure shows a four digit transmission line, the power to be
the generator that source and transmit it along with the data at the destination there or detector circuit
checks.
Any single possible error along the line provide a logic circuit for the error detector.