After designing the purity of a generator, we should examine its behavior in action, so this lecture
will synthesize the design for basis rebought.
Firstly, download the zip file containing the design files located at the lecture resources and unzip
that somewhere on your computer.
In the welcome page, click on Create New Project Icon, then in the first page of the new project,
bizarre insert parity underscored generator dash, futureless as the name and select the proper path
for the project in the second Bizerte page and at the top function name and press on the ad finds bottom.
Then go to the folder containing the design files and select the design header and source files.
In the third resource page, press on the advise button and go to the folder where you save the design
files and select to test bench header and source files in the fourth resource page.
Don't forget to choose the basic three board as the target FPGA platform.
In the generator project, you should see two design finds under the source folder and to test bench
finds under the test bench folder.
Open the design and test bench files and examine them as a design uses arbitrary production data types,
the design header file includes the API underscore that each file, also a constant variable called
W, is defined with the value of sixteen, which represents the width of the design input data.
The design source file contains a top function and unrolled for loop describes its behavior.
Notice that proper interfaces are defined in the top function, the test bench header file includes
a design header fine and defines the design top function prototype that has been Sourcefire contains
the main function, does not.
This variable is defined in the main function to keep track of the test status.
If all will be inside.
The main function generates all the design input values, then it applies them to the design and compares
the result with that of the software implementation.
In the case of any discrepancy that satisfies people will be changed and proper messages printed on
the screen.
Now we can perform the simulation to check the design functionality.
This is simulation report confirms the design functionality correctness.
Now, let's perform the synthesis process.
The report confirms that the results of the article hardbodies combination and it doesn't use any memory,
so.
In addition, the design ports correspond to the top function arguments directly.
Here, I'm going to perform the RTL CECO simulation and check the design signals for this purpose in
the simulation dialogue.
Choose the all or ports option for the dumb race feature.
After finishing the simulation, you can see the success of the design test, you can also see that
the open wave, your icon is active now.
Clicking on the icon opens the rebound away from viewer.
In the waveform viewer unfold, the design top signals to see the waveforms on the right area.
To zoom in on out the waveform, you can use the icons and the top ribbon toolbar or hold the control
key and play with the mouse or scroll.
Check a couple of inputs and outputs and make sure that the generated parity bits are correct.
This lecture is the last in this section that explained the design concepts and techniques, so the
next lecture will give you a couple of harder designs and exercises through which you review and master
the proposed techniques in this section.
This is our takeaway message, the design signals the way form can be dumped in a fine during Article
six simulation to be checked later using the pivot away from pure.
Now the question, what is the design propagation delay estimated by the Nevada test toolset?