Exelis consensuses, basic arithmetic operators into the conventional circuit without any extra work
from designers compared with designing the same circuit, an article that requires lots of efforts which
makes that tedious.
Now, the question motivated this lecture is how does a naturalist toolset synthesize arithmetic operations
on native sea data types?
The five common arithmetic operators on integer values available in Etchells are addition, subtraction,
multiplication, division and modulus.
Or reminder, these basic operators can be applied on all c C++ native data types, also on arbitrary
precision data types available in this.
Notice that C based native data types are all on eight boundaries.
Therefore, Operator Accuracy's are constrained by these boundaries.
All variables involved in an athletic operation can be of the same type, such as this example, or
they can be declared using different data types, such as the second example that utilizes three data
types, including in shorthand car specialist tools, implement these operations using automatic typecasting.
Throughout this section, I will talk about the typecasting in Etchells.
In this course, we expect that the combination of circuit implements and arithmetic operation on any
data type.
Therefore, let's have a quick look at the operations that can potentially be synthesized into combination
all circuits.
Generally, there are two types of arithmetic operators in regard to this combination of oil and pipeline.
The pipeline implementation uses a set of memory cells called flipflops to split the corresponding operation
with the long propagation delay into a few steps.
This technique is one of the main methodologies to increase design throughput.
I will explain the whole idea behind the pipeline circuits and their design methodologies in Escalus
in a separate course called digital system design, with high level sentences in FPGA sequential circuits.
There are two main constraints involved in choosing either the combination or pipelined implementation.
The first constraint is the timing.
There is a clock frequency constraint assigned to each design in revalidation.
If the propagation delay of an addition, subtraction or multiplication is less than the clock period,
then it will be synthesized into a combination or circuit by default.
Otherwise it is synthesized into the pipelined implementation.
Using a proper resource constraint is the second technique to choose between the combination of pipelined
implementations.
I will talk about this technique later in the session.
Lookup tables and Espy's are the two main Hardwell resources available on the FPGA that can be used
to implement integer arithmetic operations.
As we already know, lookup tables are the basic resources inside an FPGA to implement a combination
of logic.
Cirque de Aspies are the most complex blocks available in Xilinx of PGD, the embedded DSP blocks in
modern FPGA and high performance arithmetic computation to the FPGA.
In order to compete with async designs, they contain a few highly efficient arithmetic hardware blocks
that can be configured to implement a complex arithmetic expression.
Before explaining how to use different types of resources to implement an athletic operation in Etchells,
I should explain another key concept which is overloading.
Therefore, the next lecture will explain this concept initialised.
These are our takeaway messages that journalists will automatically synthesize arithmetic operations
on the native sea data types combination, all circuits can implement an automatic expression, lookup
tables or DSP can implement arithmetic operations.
Now, the queen of this lecture, right, a simple HLC function that receives 264, 64 bit integer values
and returns their multiplication.