The question of this lecture is, how can we describe an arithmetic expression in class to be synthesized
into a combination?
Alzaga I will focus on the clock time constraint to answer this question.
There is a clock timing constraint attached to each design in place before explaining the role of this
constraint in designing computational circuits, let's get familiar with the clock signal in general.
More details about this signal and how to generate and use that in a design are explained in a separate
course called digital system design.
With high level sentences in FPGA sequential circuits, a clock signal has a square waveform, alternating
between zero and one logic values.
The clock period determines the duration of a cycle of the clock.
In Nevada, this period is denoted by nanosecond.
The clock signal can also be defined by its frequency, which is the number of cycles in a second.
And it is the reciprocal of the clock you.
And they regard HLS new project with a window called Solution Configuration shows a default clock period
constraint assigned to the design and you can change that if it's required.
The the off the clock period is nanosecond, for example, in this figure, the clock period isn't 10
a.m. The clock period also can be determined by the clock frequency, but its unit is megahertz that
should be mentioned explicitly.
For example, in this case, the equivalent frequency is one hundred megahertz.
The clock constraint also has another parameter called uncertainty, which is not our concern in this
course as we are focusing on the combination of circuit design.
The clock of a design can have a direct impact on the final hardware structure if the total design propagation
delay is less than a clock period and the design doesn't use a memory so explicitly that HLS tool drops
the clock signal during the sentences and generates a fully computational circuit.
If the clock period is longer than the design propagation delay, the high level synthesis tool automatically
escargots the operations over more clock cycles, and some operations might need to be implemented by
using multi cycle resources.
In this case, the operations are broken into several steps by adding flipflop memory cells between
systems.
Then the clock signal is used to save the results of each step and pass them to the next.
The result of a circuit structure is called Pipeline, which is the subject of a separate course.
As I mentioned in the previous slide announcement, the entire operation can be synthesized into a single
cycle combination or circuit or a multi cycle sequential circuit using the pipeline structure.
One of the key parameters to decide this election is the relation between the design propagation delay
and the clock timing constraint assigned to the design.
Let's use the evaluation aside to demonstrate this relation.
Firstly, we need to create an Atlas project, choose a name for the project, for example, timing,
underscore constrained vehicles, then choose the name of the design top function, such as timing,
underscore constraint, then accept the ten nanosecond clock period as the design clock constraint.
Don't forget to choose the basic storyboard as the underlying FPGA finally click on the finish button
to generate the project.
Now create a new design, fight a name it timing, underscore constraint that CPPIB then other design,
top function, name timing, underscore constraint as this.
The function receives two integer inputs and returns their multiplication.
After synthesizing the design, the report shows the features of the generated combination of circuits,
the propagation delay is about eight point forty seven nanosecond.
The final circuit only utilizes lookup tables without any memory cells, which means it is a combination
of a circuit.
Also, harder ports only include function arguments.
Let's have a look at the analysis perspective, the design timing shows only one control step, so it
doesn't need any memory cell, such as flip flops to save data transferring between systems.
Now, let's change the design period construct for this purpose, go to the synthesis perspective.
And right, click on the solution one folder and select the solutions settings option now under the
sentosa settings, change the clock period from ten to five, which means the design clock frequency
would be two hundred megahertz.
Then perform the synthesis again.
If you have a look at the synthesis report, we will notice that the generator, the hardware is not
conventional anymore as it utilizes 220 flipflops and there is a clock signal in the hardware portal.
By looking at the analysis perspective, we can see that the design execution spans or five steps.
Therefore, the design requires some memory cells, such as flipflops, to transfer data between steps.
As can be seen, the synthesis process has utilized a pipeline multiplier to implement the multiplication
operator in the code.
The timing constraint is not the only parameter that impact on the result resource constraint is also
another parameter that will be explained in the next election.
These are our takeaway messages.
There's a time constraint attached to each design in each of us choosing a proper clock period supports
the Etchells to synthesize a description into a combination of Circa.
Now, the quest for this election find a proper value for the clock period in which rather rituals to
synthesize the following code into a combination of.