In addition to the clock period, constrained resource constraints also have a direct impact on the
syntheses floor to create a combination of acerca before introducing the resource constraints and adding
them to our designs.
This lecture briefly explains the computational resources in an advanced FPGA.
Traditionally, FPGA is where using logic gates to describe arithmetic expressions.
This solution is adequate for applications with a few arithmetic operations.
However, applications with complex computations require more efficient implementation techniques to
cope with this demand.
Advanced figures have introduced DSP blocks that are capable of performing high performance arithmetic
operations.
Therefore, nowadays there are two different types of resources available on FPGA to implement arithmetic
operations, lookup tables and Espy's.
In previous lectures, we understood that if pigs used lookup tables to implement logic circuits, including
logical and arithmetic operations, después are reconfigurable computational blocks added to the FPGA
architecture by winders to increase the design performance comparable to the Aztec counterpart.
A typical DP block receives a couple of inputs and then passes them through a set of predesigned, reconfigurable
addition and multiplication modules.
This figure shows a simplified design of DSB 48 hour level in the Arctic seven FPGA using bases.
Traymore almost all the data paths and computational modules inside the DSP are reconfigurable.
As a necklace designer, we don't need to know the details of the DSP blocks and how to reconfigure
them, they actually still manages all the configuration tasks for us automatically.
However, being familiar with its structure and role in implementing arithmetic expressions helps us
to guide the actual synthesis process to generate high performance art descriptions.
At the heart of a DSB, there is a multiplier that accepts a 25 bit and then 18 bits to complement inputs
and generates a 40 Tribbett to complement or result.
This multiplier receives one of its inputs via a PRISM module and gives its output to a post other module.
There are also other parts in ADP to provide enough data to implement different mathematical and logical
expression, most data points inside the DSP can be registered in flipflops.
In addition, the multiplier and additions inside the DSP can be implemented by a single stage combination
or circuit or a multi-stage pipeline such.
Let's see how a DSB can be reconfigured to perform a multiply by this attack directed acyclic graph
represents this expression Let's assume ADP, the being put feeds the multiplier directly.
And the input bypasses the other and is connected to the multiplier.
Finally, the multiplier as a result gets to the output by avoiding all the operators along the path.
It is we can also directly implement this expression.
The corresponding deck shows two levels of operations, the first level is addition, and the second
one is multiplication.
And this diagram shows the related data path in a DSP block performing the arithmetic expression.
In summary, both lookup tables and DSP blocks can be used to implement a combination of all pipeline
implementation of an arithmetic expression.
But the question is, how can we guide us into this process to choose between lookup tables and the
Espy's, the next lecture cope with this question.
These are our takeaway messages, these blogs provide an easy class computational performance for FPGA
designs.
An arithmetic expression can be implemented with lookup tables or the Espy's or a combination of both
resources.
Now the question, what is the data in the following, the speed that performs this arithmetic expression?