In the previous lectures, we talked about the intelligent addition, subtraction and multiplication
in us and how to synthesize them in divide us into different hardware structures.
In this lecture, I'm going to cover the integer division and modulus operators initialised as these
operators require special attention when it comes to synthesizing them into combination or circuits.
What is the integer division return is the caution of two integer values, the modulus returns the remainder
of the integer division.
For example, if you consider these two numbers that are four hundred and eighty seven and 32, then
they integer division is 15 and they're modulars is seven.
Integer division by a constant value is a special case in which the divisor is a fixed number, synthesizing
an integer division by a constant value generates a combination of circuit by default if the clock period
is larger than the circuit propagation delay, as can be seen in this regard.
Let's report the propagation.
DeLay is about fifteen point five four four nanoseconds and the implementation utilizes for the Espy's
and 197 lookup tables.
We can add resource constraint to the area, able to buy the division operator to the defense corps,
which is a pipeline for implementation of the signed integer division.
In this case, the results won't be a combination or circuit.
And we can see the design utilizes five percent of flipflop memory cells and the IP has to extra input
signals which are AP underscore sialic and AP underscore Oreste representing the design and research
respectively.
We want HLA synthesis synthesisers, the integer division by a variable into a pipeline circuit by default,
and if we add the resource constrained to bind the operator to the D and score, the result would also
be a pipeline.
Synthesizing the modulus operator results in a pipeline circuit in all cases.
However, if you want to synthesize the modulus of a number by a constant value into a combination of
circuit, we can use its equivalent equation like this.
Let's say that in practice, using the five other cells to learn if you're coding a science for developing
a combination or circuit.
First, let's create a new evaluation project with the name of integer underscore division, underscore
Modulus Daneshvar.
And choose integer, underscore division, underscore modulars as a top function name.
Don't forget to choose the basis three and the target FPGA.
Now, we should create a new file to describe the design function.
First of all, let's define an integer constant value.
The design top function receives an integer input denoted by a unretire as an integer output denoted
by R.
The return value is a modulus.
Now, we should add port interfaces.
Let's synthesize the code.
The synthesis report shows that the design utilizes flipflops and has two extra ports which are Klok.
Let's have a look at the analysis perspective to get more information from the inside of the synthesis
process.
As can be seen, it uses its frame operator to implement the modulus.
And this operator is implemented by pipeline circuit, which has about 35 stages.
Now let's implement the modulus functionality with division by a constant number using this expression.
To more understand the synthesis tool behavior, I will follow a step by step process to implement this
expression.
So let's consider only the division by a constant number.
If we synthesize the code, there is also this combination of.
Now, if you have a look at the analysis perspective, the division by a constant number is implemented
by basic arithmetic operators look, suspend expression and multiply the division by the constant number.
After synthesizing the code, we will realize that the output circuit is not computational.
Let's check the analysis perspective.
We see that the sentence is optimization process has used the SRM operator to implement the expression
we should find a way to stop the optimization process from using this operator for this purpose.
I define a function that implements the division.
However, as they want to tell a synthesis tool automatically in lines all the small functions, we
expect to see the SRM operator again in the synthesis report.
Let's prevent this automatic enlightening by using the inline directive with the off option.
Now, if you synthesize the code, the resulting circuit would be a combination.
We just need to complete the expression and synthesize again.
The new synthesis report confirms that the generator, the hardware is a combination.
This lecture is a class in this section that explains the design concepts and techniques, so the next
lecture will give you a couple of harder designs and exercises through which you review and master the
proposed techniques in this section.
This will take him a message I proper directives to the code can prevent the synthesis tool from applying
some different optimization techniques and generate the desired RTL hardware.
Now, the quiz question compared to the propagation delay of the first implementation for the modulus
operator with that of the last one, which was implemented by a combination of circuit.