In this lecture, we will use the Weimar dialect toolset to run the simple calculator on the basis what
you can find the project source files in the resources folder attached to this lecture.
Firstly, your view new the Atlas project with simple underscore calculator dash, listen and consider
the Basis three evaluation board and the Target FPGA.
Then create design and test bench source and halophiles.
Open the are fine then include the AP underscore in that file and define a few arbitrary production
data types, then defined the Southern segment code for the minus sign and when all segments are off.
Also define a constant array containing all the seven segment codes, four digits from zero to F..
Open the design Sourcefire defining of function, which receives five inputs and generates two outputs
at the port interfaces.
Call it three functions explained in the previous lecture that our operations extract digits and display
digits.
Finally, send all the inputs from slide switches to daylilies.
Notice the way of concatenated for inputs and unused bit that is assigned to zero.
Here, we should explicitly use the typecast AP underscore in one.
Otherwise, the stool concatenated A and B and feels the rest of the bits with zero, which is not desire.
Now we should define the three functions.
We create a source file for each function.
Create a file called operations that sweep under the design source folder, then write the operations
function code, which contains a switch case statement to select the proper operation here.
I have used a 10 bit sine arbitrary precision data type for the result as I am expecting to consider
more operations later, such as multiplication.
You can use fewer bits for the result if you wish anyway.
Detlor synthesis tool optimises the hardware and removes old unused bits.
Create a file called extract underscored digits that slip under the design source folder, now copied
extract, underscored digits of function code.
Here, the code defines division by a constant number as a sole function which cannot be inline during
the synthesis optimization.
The function body detects the result sinus and extracts the three digits according to the display mode,
which can be hexadecimal.
For implementing the last stop function, create a new file under the design source folder with the
name of display underscore digits that.
Now copy the corresponding code into the created file.
You can find the project source files.
Are the resources attached to this lecture or the course GitHub site.
The code contains a function called seven, underscore Sigmon, underscore Daejeon, underscore code
that returns the code corresponding to a received digit.
The code also contains the function that sends the proper data and value to the seven segments.
For example, if select underscored digit is zero zero zero one, which means the user has pressed the
left push button, then the function will send the first digit code to the first down segment and activate
that by the one one one zero control value.
The code does the same for the other digits just for the sine digit.
It first checks that these three, which represents the sign and then sends a proper seven segment code.
If none of the push buttons is pressed, then all seven segments are of.
Now, let's add the prototypes of the defined functions into the design Gadaffi.
We should now develop the test flights, going to the test bench header file and include the design
header file and other design top function prototype in the source that speechify defined the main function.
Firstly, we need to declare a couple of variables to be used later.
Then we use five minutes and loops to go over all the possible input values by using the following.
This is we should prepare the design top function arguments.
Notice that as I assume that the users only press one push button at the time the selected.
You should have only one bit with the value of one.
Therefore, I have used the left shift operator to implement this restriction.
Then we should apply the data to the design and its equivalents, software implementation.
So let's define the software implementation.
Create a new source fine with the name of simple underscore calculator, underscore software that sweep
under the test bench folder, then copy the function code into the file.
Finally, in the test bench, main function, comparative results and report any possible error.
Now, we are ready for this simulation after performing this simulation.
The report confirms the design functionality correctness.
After doing this simulation successfully, you can perform the high level synthesis, the design report
shows that the resultant Archil hardware has used flipflops and is not a combination of.
To find the problem, let's have a look at the analysis perspective.
That's can be seen, the design execution requires eight steps to finish, therefore the short design
clock period constraint can be the source of the problem.
Let's increase the design clock period constrain.
As a devout Catholic period, constraint is 10 and our design requires eight steps to complete, let's
change that from 10 to 80 and synthesize the code again.
Now, the design is fully confidential.
To make sure that they generated RTL design is correct, let's perform the RTL sequence simulation.
After finishing the simulation successfully, we can package the design into an article IP to be used
later in interview are the Project for Logic Synthesis and if BGB this third generation.
To generate FPGA bitstream, we need a the project, so let's create a the project with the name of
simple underscore calculator dashboard and consider the basis three as a target FPGA platform.
Then create a block design in order to use our design IP, we should add that to the repository.
Now we can instantiate the IP and add that to our design, make the ports external and change the names
if you wish.
Now, let's define the constraints you can find them in the project source files attached to this lecture.
Before generating the bitstream first, we should perform the generate output product task.
And credentialled rapper.
After generating the bitstream successfully, we can program the board and examine the design functionality
on the board.