Despite all the benefits of the FPGA technology, FPGA-based design can be a real challenge. 1
Implementing logic circuits and computing algorithms on an FPGA requires its own design flow and 2
techniques. 3
This lecture briefly explains different levels of abstractions in the FPGA design flow. 4
Low-level design flow based on logic gates such as AND, OR and NOT was the first design flow for implementing 5
simple logic circuits on FPGAs. 6
Using this approach, designers can implement simple circuits on small FPGAs. 7
With the increase in the number of resources available on new FPGAs and their high design capacity, 8
Register Transfer Level (RTL) design approach became a standard which still is used by many designers. 9
VHDL and Verilog are the two widely adopted RTL languages among the designers in industry and academia. 10
The high demand for computational power and the unique features of advanced FPGAs have motivated 11
designers to propose a higher-level design approach to map complex algorithms on an FPGA with less effort. 12
Therefore, High-level synthesis (HLS) design techniques, in which software languages such as C/C++ 13
are used for design description is proposed. In this design approach, 14
the HLS toolsets are responsible for automatically synthesising the C description into an efficient 15
hardware circuit. 16
Hardware Design Languages (HDLs) such as VHDL and Verilog are the standard way for describing a design at 17
gate-level or RTL. These languages are used to describe the functionality and timing of a hardware 18
circuit. 19
There is also a close relationship between the language statements and the hardware resources available 20
on an FPGA. 21
These features make the design process tedious as designers should have in-depth knowledge about the 22
hardware timing and resources. The HDL languages are usually compared with the assembly languages 23
in software. 24
The HLS uses high-level software-based languages that are used to describe the design functionality. And 25
it is the responsibility of the HLS toolset to extract the timing and hardware resources, automatically. 26
This approach helps the designers with low hardware knowledge to map complex algorithms and applications 27
on a given FPGA. 28
Therefore, rapid advances in FPGA applications have been possible with using High-Level Synthesis techniques. 29
HLS is pretty hot these days, and it is a topic which is definitely here to stay. 30
HLS is a set of coding styles, optimisation techniques, and synthesis tools to map a software function 31
onto a hardware platform such as FPGA. 32
Notice that using HLS with specific coding styles and optimisation directives enables us to 33
map almost any logical or mathematical function on a given FPGA. 34
Several companies are using HLS techniques to design their hardware products including Nvidia 35
in designing Tegra embedded GPU, Google in building VP9 encoder/decoder, Qualcomm in image processing 36
AMD in designing microprocessors, ST Micro in implementing H.265. 37
Both FPGAs and CPUs can be used to implement logical and computational functions. But what are their 38
differences? In the following lecture, 39
I briefly explain the underlying difference between these two computing platforms. 40
The takeaway messages from this lecture are: HLS is a new hardware design approach, and it is a 41
topic which is definitely here to stay. HLS is the preferable design approach to map a complex algorithm 42
on a given FPGA. HLS can also be used for designing traditional logic circuits 43
Now, the quiz of this lecture, 44
Which design level is more suitable for implementing a machine-learning algorithm on an FPGA? And Why? 45
Gate level based on VHDL language, RTL based on Verilog language, HLS based on C/C++