Both FPGAs and CPUs can be used to implement logical and computational functions. But what are 1
their differences? Here, 2
I am going to focus on answering this question and point out the main differences that help us to distinguish 3
between FPGA and CPU coding techniques. 4
A CPU is a computing platform with a fixed hardware architecture controlled by a set of commands or 5
instructions. This fixed hardware architecture is generic enough to perform any logical or algorithmic 6
function as long as it is compiled into the CPU instructions. On the other hand, an FPGA is a computing 7
hardware platform with no predefined hardware architecture. 8
Similar to the CPU platform, it can host almost any logical and mathematical function. 9
However, the synthesis tool should translate a C/C++ program into a hardware architecture composed of 10
a few hardware modules. 11
Therefore, each C/C++ program has its own dedicated optimised hardware architecture. 12
This dedicated architecture leads to high-performance execution for some algorithms on the FPGA. 13
The main difference between CPU and FPGA in running an algorithm is how statements are executed. 14
A typical CPU compiler translates a C function into an assembly language or machine code. Then CPU 15
fetches these codes from memory and executes them sequentially. 16
Therefore, sequential execution is an intrinsic feature of a CPU. For adding parallelism to the CPU 17
execution, 18
the corresponding architecture should be modified. In contrast, an FPGA synthesis tool translates 19
a C function into a set of connected hardware blocks that exchange data. 20
These hardware modules will be activated as soon as they receive their required data. 21
Therefore they can perform operators in parallel. In other words, 22
parallelism is an intrinsic feature of FPGAs. 23
The concurrent statements in a C code, which have no data, resource or control dependencies among them, 24
can be run in parallel on FPGA. 25
Therefore, the concepts of concurrency and dependency among statements are very important in coding 26
an algorithm for FPGA. Along this course, 27
I will explain how to detect the statements concurrency and describe them in the C code using specific 28
coding styles and compiler directives. 29
Let’s consider this very simple computing architecture as a CPU that can perform two instructions: reset 30
a variable and adding two numbers. 31
It consists of a memory that keeps data, an Arithmetic Logic Unit (ALU) which performs addition, 32
a register to keep the result and finally fixed connections between these elements. 33
The memory has two lines to address a memory cell. 34
The register has two signals: reset and load. 35
If we put the logic value 1 on the reset signal, the register value will be 0. 36
Let’s assume that the CPU is going to run this simple C code. 37
For this purpose, the code should be translated into the assembly or machine code. 38
The machine code represents the sequence of the hardware structure signals to perform the original C code. 39
Let’s follow the CPU execution steps. Here, 40
I have ignored the instruction fetch for the sake of simplicity. In the first step, the register that keeps 41
the answer is set to zero. In the next step, the first data in the memory (that is c1) is added to 42
register a. In the third and fourth steps, 43
the c2 and c3 values are accumulated to the a resister. 44
Now let’s study the execution of the same C code on an FPGA. To implement the C code on an FPGA, the 45
synthesis tool should translate that into a hardware circuit. 46
This figure shows such a circuit, which consists of two adders. 47
There are two steps to find the result. 48
In the first step, two c1 and c2 values are added, and in the following step, the result of 49
the addition is added to the c3 value to get the final answer. 50
Now, after understanding the execution mechanisms in CPU and FPGA platforms, do we need to learn the 51
internal structure of an FPGA to implement a circuit or algorithm in HLS? 52
I will cope with this question in the next lecture. But for a short discussion: the internal structure 53
of an FPGA is invisible to the users, so design tools take care of them. 54
However, having a basic knowledge of the internal structure and different resources inside an FPGA 55
helps designers to understand better the tools reports in order to provide an efficient design. 56
These are the takeaway messages: 57
Whereas CPUs typically execute instructions sequentially, FPGAs run then in parallel 58
Understanding the instruction dependency is important in FPGA to exploit parallelism. 59
Now the quiz question. This code shows a simple computation program. 60
The hardware structures for the CPU and FPGA platforms are shown in these figures. The CPU computing structure 61
consists of an ALU and a register. 62
The FPGA computing structure connects three adders consecutively to perform the task. Show the execution 63
steps of the code on the CPU and on the FPGA.