Firstly, the question for this lecture. 1
Do we need to learn the internal structure of an FPGA to implement a circuit or an algorithm in HLS? 2
The internal structure of an FPGA is invisible to the users, so design tools take care of them. 3
However, having a basic knowledge of the internal structure and different resources in the FPGA helps 4
designers to better understand the tools’ report in order to provide an efficient design. 5
More details of the FPGA architecture are explained throughout the course whenever we are going to use 6
them. 7
Let’s start with creating a big picture of a typical FPGA structure. 8
Conceptually, an FPGA comprises of two layers: application and configuration layers. 9
The application layer contains all the hardware modules that can be configured and connected together to implement an 10
algorithm or a function. 11
After configuring this layer, we can apply the input data and get the generated outputs. 12
The configuration later consists of a set of memory cells used to configure the application layer modules. 13
The configuration data saved in this layer is call bitstream and is generated by synthesis tools. 14
The main role of an FPGA synthesis tool is converting a design description into an FPGA bitstream. This process 15
requires several optimisations and code transformation tasks. 16
The generated bitstream is used for configuring the FPGA. Then the configured FPGA can be used in a real 17
application to perform the desired algorithms or functions. 18
Traditionally, an FPGA is a collection of the following building blocks: Loop-up-tables 19
(LUTs): which are used to implement logic operations 20
Flip-Flops (FFs): these are registers (or small temporary memories) to save the LUTs’ outputs. 21
Connection network: which connects resources on an FPGA together. Input/Output (I/O) pads: to get data 22
in and out of the FPGA 23
Let’s talk about lookup tables: A LUT can be configured to implement a logical function 24
or expression. A logical unction is an expression that only contains logical operators, which are AND, 25
OR and NOT. The AND and OR operators are binary, which means they receive two operands (also known as variables 26
or inputs). 27
The NOT operator is unary, which means it applies on a single variable or input. A truth table 28
can represent the functionality of each gate. 29
This table contains the gate’s output values for all combinations of its input logic values. 30
To implement a logical expression, a typical lookup table keeps the output values for all combination 31
of the expression’s inputs. For example, this is an AND logic or gate. A lookup table that implements 32
this gate keeps all the values in the last column of the gate truth table. 33
Then it needs two inputs to address each value. 34
This logical expression has three inputs. Then its truth table has 8 entries. A lookup table 35
should keep all the values in the last column. And it needs three inputs to distinguish among them. 36
How does a LUT work in an FPGA? 37
The next video copes with this question. 38
The takeaway messages are: A traditional FPGA consists of LUTs, FFs, I/O pins 39
and finally a network connecting these elements 40
All these components are reconfigurable. 41
As the quiz question, I want you to find the LUT content for the following logic expression.