Xilinx evaluation is a toolset that we are using throughout this course here, I'm going to briefly 1
explain some of their features. 2
More details of each feature will be described whenever we use them along the course. 3
Xilinx Vivado-HLx consists of several tools that are used to describe, simulate, debug, and synthesise 4
a design at a different level of abstractions to be implemented on the Xilinx FPGAs. 5
Each tool performs a specific task. 6
In this slide, I am going to give you a big picture of the design flow. 7
The main goal of this software tool is converting a hardware design description into the final FPGA 8
configuration. 9
Several languages, including VHDL/Verilog, SystemC, C/C++ and OpenCL can be used to 10
describe a hardware design. 11
In this course, we focus on C/C++ as a high-level description language. 12
The first step is the design capture in which the design description is verified, and possible errors 13
are reported. 14
The capture process mainly focuses on the linguistic syntax and semantics of the hardware modules, 15
connections among them and their ports. 16
After writing the code, simulation is an optional 17
but essential step. Simulation is one of the main debugging techniques that designers spend most 18
of their time (almost 70%) to verify their codes. 19
There are different levels of simulation provided by Vivado-HLx such as high-level C simulation, 20
low-level HDL simulation and hardware-software co-simulation. Whereas the high-level C simulation can be 21
used for verifying the functionality of a design, 22
the low-level HDL simulation can be used for functional correctness as well as cycle accurate verification. 23
The co-simulation integrates the software and the hardware parts in order to bring the cycle-accurate verification 24
into the high-level synthesis design flow. 25
In this course, we rely on high-level C simulation and co-simulation to debug our designs. Code analysis is 26
the primary step before applying synthesis optimisation techniques. Data and control dependencies, 27
timing and hierarchy analyses are the most important tasks in this step. 28
These tasks help the next step to apply synthesis optimisations more efficiently. 29
Note that, developing the design code to ease the code analysis can improve the final design performance. 30
In HLS design flow, understanding the data and control dependencies among statements plays a crucial 31
role in developing an efficient code. 32
Therefore, throughout this course, I will try to easily explain these dependencies and different code 33
development techniques to help code analysis step. Synthesis is the most important part of the Vivado-HLx 34
design suite. 35
Generally, two levels of synthesis are available: high-level synthesis (HLS) and logic synthesis (LS). 36
While HLS translates a C/C++/SystemC/OpenCL description of a design into its equivalent 37
RTL, 38
LS converts the RTL description into a netlist of logic gates. 39
High-level synthesis is the main subject of this course, and I will talk about some of its techniques 40
used for digital system design in future lectures. 41
The implementation step uses the FPGA library and building-blocks to implement the netlist generated 42
by the synthesis step. 43
This step performs all tasks necessary to place and route the netlist onto device resources. 44
The last step is the bitstream generation and programming. 45
This step generates the configuration file (also known as a bitstream) that can be used to program 46
an FPGA. 47
Concentrating on the HLS design flow will be our next step. 48
These are the takeaway messages: The Xilinx Vivado-HLX toolset is used for developing a hardware 49
circuit for the Xilinx FPGAs 50
In our course, we use this toolset to convert a C/C++ description of a design into the FPGA bitstream file 51
file. 52
Now the quiz question. What is the difference between C-simulation and co-simulation in HLS?