After having a big picture of the design steps in the Xilinx Vivado suite HLx toolset, we should 1
know the specific tool that performs each step. 2
Vivado design suite-HLx consists of two main software tools: Vivado-HLS and Vivado. 3
The HLS design flow 4
starts with Vivado-HLS software. 5
This software gets your design description in C/C++ and translates it into the equivalent HDL description. 6
The Vivado-HLS 7
software performs five subtasks including Design capture, C-Simulation, HLS synthesis, Co-Simulation 8
and Package generation 9
The generated package or IP should be imported into Vivado design suite software for logic synthesis 10
and then bitstream generation. 11
Vivado consists of five steps including: Design capture, RTL simulation, Logic synthesis 12
Implementation, and finally Bitstream generation 13
The generated bitstream can be used to program the target FPGA. 14
Let’s have a close look at the Vivado-HLS IDE. After running the Vivado-HLS software, 15
an eclipse-based IDE appears on the screen. 16
The whole design is defined under a project which its structure is represented in the Explorer view. 17
The main part of the project structure is the source and testbench folders where you can add a new source file 18
or delete an existing file from the project. 19
A proper editor allows you to write your code and find the typos. 20
All the HLS tasks can be invoked by clicking on the proper icon on the toolbar. Four main icons are corresponding 21
to C-simulation, Synthesis, Co-simulation, Export RTL (or IP generator) 22
The generated IP by the Vivado-HLS should be imported into the vivado design suite 23
for logic synthesis. Vivado-IDE provides a project-based process. 24
You can use Vivado IDE to perform all tasks from design definition to the bitstream generation. 25
The flow navigator pane contains a list of all these tasks. 26
The top section in the flow navigator is for changing the project settingssuch as adding source 27
files, defining the parameters of target 28
FPGAs, simulation, synthesis, implementation, bitstream and lots of other features that we explain 29
parts of them along the course. 30
The second section “IP integrator” is used for defining the design space and integrating the generated 31
IP by Vivado-HLS into the design. The RTL simulation is accessible in the third section. 32
Sections 4 to seven are used for RTL analysis, logic synthesis, Implementation and bitstream generation. 33
Now the question is, How can we install our software and hardware components and prepare our lab 34
environment? In the next lecture, 35
I will answer this question. 36
These are the takeaway messages from this video 37
To use C/C++ language to design hardware, targeting Xilinx FPGAs, we should use two different software 38
tools. 39
Vivado-HLS and Vivado. 40
The Vivado-HLS converts the C/C++ description to the equivalent HDL code and the Vivado receives the HDL code 41
and generates the final FPGA bitstream. 42
Now the quiz questions, 1- What are the design tasks in the Xilinx Vivado-HLS software? 43
2- What are the design tasks in the Xilinx Vivado software?