How to use the Xilinx Vivado to generate the FPGA bitstream? The generated RTL IP by the Vivado-HLS 1
toolset requires the logic synthesis process to be converted to an FPGA bitstream. 2
The Xilinx Vivado Suite 3
can do this process. 4
In this video, I am going to use this tool to create the FPGA bitstream file. 5
Now run the Vivado IDE which can be done by double-clicking on the related icon on your desktop 6
or clicking on the program link in the "Start Menu" in Windows OS. If you are using a Linux based system, 7
you can run vivado command for this purpose. 8
After running the Vivado, the first page appears where you can start managing your project. 9
On the Quick Start section, you can create a new project or open an existing project. 10
There is also a list of the recent projects on the right-hand side that you can choose from and continue 11
working on your previous projects. 12
Let's create a new project by clicking on the "Create Project" link. Then the "create new project" wizard 13
starts. Press Next. 14
Select a name for your project and set a destination path for that. 15
It is a good practice to select the "Create project subdirectory" option. 16
Click next to get to the next step. 17
Choose RTL project, as we don't have any source file in this course select "Do not specify source 18
at this time" option. And click Next. Choose the target FPGA or Board. Click on the board, choose digilentinc.com 19
from the vendor list and then select the Basys3 Board and press 20
Next, After reviewing the project summary, press on the Finish button to create the project. As we are 21
going to use the IP generated by Vivado-HLS and probably some of the IPs from the Xilinx library 22
and we don't have any RTL source file, so we follow the Xilinx IP integrator design flow. 23
This design flow starts with creating a block design. For this purpose, click on the "Create Block Design" 24
link on the left hand-side pane. 25
You can choose a new name for the design or keep the default. 26
Let's keep the default. The Diagram 27
window appears to draw our design. 28
First, we make our generated IP by Vivado-HLS accessible for the 29
Vivado IP integrator. For this purpose, 30
right-click 31
anywhere on the Diagram area and choose "IP settings…" from the drop-down menu. 32
The setting window appears. Select IP->Repository from the left-hand side 33
list of options. In the IP Repository section on the right-hand side, 34
click on the plus icon. 35
Find the Vivado-HLS directory that you have already created for the basic_output project. 36
If you have multiple solution folders under the Vivado-HLS project directory, choose the desired 37
one and press Select. Viviado searches the solution folder for any possible IP available and adds the folder 38
to its repository. Click OK in the Add Repository dialog box. Then press OK to get back to the Vivado IDE. 39
Now press the plus singe in the middle of the Diagram area or right-click anywhere on the area and select 40
Add IP from the drop-down menu. In the search field, 41
write the name of your IP, which is basic_output in this lab. 42
Double click on the IP name to add that to our design. 43
Our IP with one output port appears in the Diagram area. 44
Select the port and then right-click and select “make external” option. 45
You can change the name of the port and give that a more convenient name. 46
As this port drives the LEDs, we change the name in the external port properties view to led. Notice that 47
this port is a vector of 8 signals. 48
Then the individual signals can be addressed by led[0] to led[7]. To connect the design external- 49
port to the FPGA pins that are connected to the LEDs on the board, 50
we should create a constraint file to define a set of physical I/O pin constraints. 51
For this purpose, click on the Source tab on the left-hand side of the diagram area. Then right- 52
click on the Constraints folder and select "Add Sources …" option. 53
In the add sources dialog, make sure that "Add or create constraints" is selected then press Next button. 54
and then click on the "Create File" button. 55
Here you can choose a file name in the dialog box. For example, basic_output then 56
click OK and Finish. 57
The XDC file editor will be opened to add your constraints. Instead of adding constraints from scratch, you can use 58
the related XDC file provided by the board vendor and uncomment and modify the required constraints. 59
Connect to digilent gitub site at https://github.com/Digilent/Basys3 60
then go the Resources/XDC path, open the Basys3_Master.xdc file and copy all its 61
contents into the xdc file in your vivado project. To connect our design output to 8 LEDs, 62
we uncomment the first 8 LEDs constraints in the LEDs section. 63
The signal name in the constraints is LED, which is exactly the same name as the external port in 64
our design. 65
So, no other changes are required. 66
Right-click on the design name in the Sources tab and click on the "generate output products…" option. 67
This process creates some internal files and structures required for the rest of the Vivado design flow. 68
The Generate Output Products 69
dialog will be opened. Accept the default values and click on Generate button. 70
Then right-click on the design name in the Sources tab again and select the "Create HDL Wrapper…" option, 71
which creates an HDL top file that encompasses our design . 72
Now we are ready to generate the FPGA bitstream. ON the left-hand side pane, click on Generate Bitstream 73
under the PROGRAM AND DEBUG section. 74
It takes a couple of minutes to generate the FPGA bitstream. 75
After generating the FPGA bitstream, we are ready to program our FPGA board. In the next lecture, 76
I will explain that. 77
These are our takeaway messages. To be able to use the IP generated by Viviado-HLS in the Vivado IDE, 78
we should add that to the IP repository. 79
The list of constraints provided by the Basys3 board vendor can be used and modified to add 80
constraints to our design targeting this board. 81
Now, the quiz question. Keep the default port name in the design, then modify the required constraints 82
and generate the FPGA bitstream.