In this video, I will show you how to use the Xilinx Vivado–HLS toolset to implement the simple 1
LED controller explained in the previous lectures. 2
Here, I'll walk you through the basic steps of developing a hardware design with Vivado-HLS. 3
Therefore, by the end of this lecture, you will practically learn how to use Vivado-HLS to describe 4
a hardware module in C/C++. 5
These are the steps that we are going to follow In Vivado-HLS, we Create a project, Add a source file, Perform 6
High-Level Synthesis, Generate IP. 7
Let's get started. First, run the Vivado-HLS IDE which can be done by double-clicking on the related 8
icon on your desktop or click on the program link in the "Start Menu" in Windows OS. 9
If you are using a Linux based system, run vivado_hls command to start the Vivado-HLS IDE. 10
After starting the Vivado-HLS, it shows you the welcome screen where you can see the options to create 11
or open a project. If you don't see the welcome screen for any possible reason, you can open that 12
by going to Help menu and select the Welcome… option. 13
You can also find your previous projects in the "Resent Projects" area. 14
If this is the first time you run the vivado-hls, the welcome 15
screen doesn't show this part. 16
A few links to the related documents are also shown in the welcome screen. 17
Here, we start by creating a new project. For this purpose, 18
click on the "Create a New Project" icon. Then the create new project wizard starts. The first step 19
asks you to choose a name for the project and modify the project location. 20
The name of the project will also be the name of the folder that contains the entire project files. 21
The next step asks you to add design files if they already exist. 22
This page also asks you the name of the "top function" which would be the name of the hardware module 23
entry function. 24
Notice that each hardware module can only have one top function. 25
All other functions in the design should be called through this top function using a possible hierarchy 26
of function calls. 27
If you don't know the top-function name or you haven't prepared the design files, just click next, as 28
we can define that later. 29
The next step asks you to add the testbench files. 30
As for the sake of simplicity we don’t have the testbench file in this first lab, click next to get to 31
the "Solution Configuration" page. 32
In this page, you can configure the design clock and define the target FPGA. 33
Here you can choose a solution name which would be the name of the subfolder inside the project folder 34
that keeps all the files generated by the HLS flow. 35
As we only consider the combinational circuits in this section of the course, you can ignore the 36
clock-related parameters in this page. 37
Choosing the target FPGA is necessary. 38
Click on the ellipsis icon. 39
Here you can select a specific FPGA or a particular board. 40
Click on the board, from the vendor menu, choose the digilentinc.com and find the Basys3 in 41
the list of boards. Pressing the Finish button opens 42
the Vivado-HLS graphical User interface or GUI. The Vivado-HLS GUI consists of four panes 43
as default. 44
We will explain them as we use them. 45
We start with the project explorer view on the left. 46
If you cannot see this pane, go to Window menu and select Window->Show View->Explorer 47
In the Explorer view, 48
you can see the list of objects associated with our project. 49
It contains, the default included hearer files, 50
source folder which is empty at this point, Test bench folder which is also empty, and the Solution 51
directory Which only contains the constraints files at this step. We'll explain that later. To add a design 52
file 53
right 54
click on the source folder and select the "New file …" option. Choose a file name, for example, "basic_output.cpp" 55
And press the Save button. 56
A proper editor opens the file which is empty at this stage. Start and add the basic_output C function. The 57
function has an output argument, so it should be defined as a pointer. 58
We are using the 8-bit unsigned char as its data type. 59
The function body has just one line which put the constant binary value of 11110000 60
to the output argument. 61
Now, we should add HLS pragmas for the output port and function block. 62
There are two ways to add pragmas to the code 63
The first is adding manually to the source code 64
The second approach is using the Directive view on the right-hand side pane. 65
If you cannot see this View, select Window->Show View->Directives from the menu bar. 66
There are two groups of pragmas. The top-level function pragma which adds some control signals to the 67
synthesised hardware 68
And the port-related pragmas. As our design is a simple combinational circuit, these two groups 69
of pragmas do not define a specific interface. To add the function level pragma, right-click 70
on the function name in the Directive View. 71
Then select "Insert Directive" from the drop-down menu. 72
Then select the INTERFACE directive. In the options part, choose ap_ctrl_none as the mode.Choose 73
the source file in the destination section. Then press the OK button. A new pragma should be added to 74
the source file under the function definition. Then right-click 75
on the argument name in the Directive view and select the "Insert Directive…" option. 76
Then select the INTERFACE directive, 77
In the options part, choose ap_none as the mode. Make sure that the "Source File" is selected as the Destination. 78
Then press the OK button. Another pragma should be added to the source file. 79
Now you can save the file. 80
After saving the file, we are ready for performing the synthesis. Click on the synthesis icon. 81
You can follow the report messages in the Console view in the lower pane. 82
It takes a couple of seconds to finish. 83
At the end of the synthesis report, you can see a summary of the hardware interfaces which should 84
contain only one port with ap_none protocol. After synthesis, we can wrap up our design into a package 85
by pressing on the "Export RTL" icon on the toolbar. 86
The Export RTL page is opened. 87
Accept the default values and click on the OK button. 88
The RTL package or IP will be generated after a couple of seconds. 89
Now we are ready to use this IP in the Vivado IDE to generate the final bitstream. 90
Now that we have transformed our HLS design into an RTL IP, the question is 91
How can we integrate the IP into the final design to program our target FPGA? The next lecture will 92
cope with this question. 93
The takeaway message from this lecture is 94
Main tasks for developing a design in Vivado-HLS are Creating a project, Writing the design functionality 95
in C/C++, Synthesising the design, Generating the corresponding RTL IP. 96
Now the quiz question Use the following C function as the LED controller that returns the LED values, 97
then generate the corresponding IP using the Vivado-HLS.