How can we convert a hardware IP generated by Vivado-HLS into the FPGA bitstream? In order to generate 1
generate the FPGA bitstream file, the Xilinx Vivado toolset should be used. In this lecture, 2
I am going to explain the basic steps of how to use Vivado toolset to generate the final FPGA bitstream. 3
After having the hardware IP, we can import that to the Vivado design suite. Our IP only has an output 4
port which is an array of 8 binary signals. As shown in this slide, 5
I’ve changed the name of the port to led as they will be connected to LEDs on the board. 6
The led[7:0] 7
array represents the eight connection signals inside the FPGA. 8
But, what should we do to connect these internal signals into the FPGA pins connected to the LEDs on 9
the board? 10
We need eight connections to connect design output ports into U16, E19, U19, V19, W18, U15, U14 and 11
V14 FPGA pins. 12
This is the place that the concept of physical constraints comes into play. 13
Design constraints define the requirements that must be met by the compilation flow in order to make 14
the hardware design functional on the board. 15
As we know, a typical FPGA has several I/O pins to communicate with external modules. A 2D coordinate 16
index indicates each pin location. As part of the FPGA reconfigurability, 17
these pins can provide different voltage levels and electronic signalling based on the standard assigned 18
to each pin by the designers. 19
For example, based on a specific I/O standard, a pin can provide 3.3v, 2.5V, 20
or 1.8v for the high logic value or deliver a different level of current 21
to drive external devices. 22
Also, a single-ended or differential I/O standard can be assigned to an FPGA pin. For example, 23
LVCMOS33 is a 3.3 volt, Low Voltage CMOS and single-ended I/O standard. To connect 24
each design port to 25
an FPGA pin, two properties should be defined: pin location and standard. The I/O constraints can determine 26
the location and standard of each FPGA I/O pin connected to a port in a design. 27
The Xilinx Viviado toolset uses the TCL language to describe an I/O constraint. This constraint command 28
has four fields: 29
set_property keyword , , and 30
For example, for the first connection in our simple LED controller, two constraints should be defined 31
using this format. The location and I/O standard. 32
Usually, board vendors provide a list of all FPGA I/O constraints in a file with .xdc extension that 33
can be used by designers. 34
The BASYS3 board also has such a file called Basys-3-Master.xdc that can be found on its 35
vendor GitHub site. 36
This file contains the constraints for switches, leds, 7-segments and other hardware connected 37
to the FPGA. 38
Note, in the original files all constraints are commented by #. 39
All the constraints defined for the lower 8 LEDs are shown in this slide that can be used after 40
uncommenting the desired constraints and change the object names. 41
Here, all required constraints are uncommented. As we used the led as the port name, the object names 42
have been remained unchanged. 43
Now that we know the basic concept of integrating an IP into the Vivado Suite toolset, We should practically 44
use the Xilinx Vivado to generate the FPGA bitstream for our LED controller design. 45
The next lecture will explain this process. 46
These are the takeaway messages. To connect the IP ports into the FPGA pins, 47
we should define some constraints. 48
The main constraints determine the pin location and pin electrical standard. 49
Now the quiz, question. How many constraints in total should be added to our design in Vivado toolset?