Using the Vivado-HLS toolset in this lecture, we are going to developing our LED controller 1
and generate the corresponding hardware IP. 2
For this purpose, let’s open the Vivado® HLS Graphical User Interface (GUI) 3
Now we should first create a new project in Vivado-HLS. Set the name of the project to basic_input_output-vhls 4
basic_input_output-vhls 5
And select a proper path for the project. 6
Notice that the Windows operating system has a 260-character limit for the path length, which can affect 7
the Vivado tools. To avoid this issue, use the shortest possible names and directory locations. 8
Alternatively, you can use the Linux OS. 9
Set the top function name to basic_input_output And select the Basys3 10
board as the target platform. 11
Create a new source file and name it basic_input_output.cpp 12
Write a C function that returns void, and accepts two arguments, the first one is used as an input, and the 13
second one is used as an output. 14
So the second one should be defined as a pointer or a C++ reference. 15
In the function body, assign the input to the output. 16
Now we should define argument interfaces. For this purpose, let’s go to the directive view 17
and add the ap_ctrl_none interface to the top-level function. This interface 18
doesn’t add any extra signal and protocol to the hardware module block. Then, assign the ap_none 19
interface to both arguments. 20
This will not add any signals to the corresponding ports. And ports are synthesised as simple wires. 21
Synthesise the code and check the synthesis report. In the last parts that are the interface summary, 22
you should only see the two arguments as RTL ports. 23
If you notice other signals and ports, you have not added proper interfaces using pragmas to the top- 24
function or arguments. 25
After successfully synthesising the code, click on the Export RTL icon in the toolbar to generate 26
the hardware IP. Now we are ready for integrating this IP into a Vivado project for logic synthesis. 27
In the next lecture, we will create our LED controller project and generate the FPGA corresponding bitstream 28
and examine the design on the Basys3 board. 29
Basys3 board. 30
These are our takeaway messages. Two groups of interfaces should be added to the top-function in an HLS 31
design Argument interfaces , And top-function block interfaces. 32
If you don’t add any of these interfaces, the Vivado-HLS considers the corresponding default interface 33
Use the following C function as the LED controller that returns the stratus of the eight input switches, then generate 34
the corresponding IP using the Vivado-HLS.