0
1
00:00:01,620 --> 00:00:06,720
Using the Vivado-HLS toolset in this lecture, we are going to developing our LED controller 
1

2
00:00:06,720 --> 00:00:08,790
and generate the corresponding hardware IP.
2

3
00:00:11,930 --> 00:00:16,520
For this purpose, let’s open the Vivado® HLS Graphical User Interface (GUI) 
3

4
00:00:18,570 --> 00:00:25,080
Now we should first create a new project in Vivado-HLS.
Set the name of the project to basic_input_output-vhls
4

5
00:00:25,080 --> 00:00:27,660
basic_input_output-vhls
5

6
00:00:28,640 --> 00:00:30,850
And select a proper path for the project.
6

7
00:00:33,180 --> 00:00:40,490
Notice that the Windows operating system has a 260-character limit for the path length, which can affect 
7

8
00:00:40,500 --> 00:00:46,200
the Vivado tools. To avoid this issue, use the shortest possible names and directory locations. 
8

9
00:00:46,390 --> 00:00:49,200
Alternatively, you can use the Linux OS.
9

10
00:00:51,380 --> 00:00:57,260
Set the top function name to basic_input_output
And select the Basys3 
10

11
00:00:57,260 --> 00:00:59,150
board as the target platform.
11

12
00:01:12,650 --> 00:01:18,250
Create a new source file and name it basic_input_output.cpp
12

13
00:01:21,630 --> 00:01:28,320
Write a C function that returns void, and accepts two arguments, the first one is used as an input, and the 
13

14
00:01:28,330 --> 00:01:30,110
second one is used as an output. 
14

15
00:01:30,750 --> 00:01:35,340
So the second one should be defined as a pointer or a C++ reference.
15

16
00:01:50,440 --> 00:01:53,410
In the function body, assign the input to the output. 
16

17
00:02:00,700 --> 00:02:05,950
Now we should define argument interfaces. For this purpose, let’s go to the directive view
17

18
00:02:10,150 --> 00:02:17,620
and add the ap_ctrl_none interface to the top-level function. This interface 
18

19
00:02:17,740 --> 00:02:24,700
doesn’t add any extra signal and protocol to the hardware module block.
Then, assign the ap_none 
19

20
00:02:24,700 --> 00:02:26,740
interface to both arguments.
20

21
00:02:26,890 --> 00:02:33,460
This will not add any signals to the corresponding ports. And ports are synthesised as simple wires.
21

22
00:02:52,760 --> 00:02:58,750
Synthesise the code and check the synthesis report. In the last parts that are the interface summary, 
22

23
00:02:59,150 --> 00:03:02,000
you should only see the two arguments as RTL ports. 
23

24
00:03:02,840 --> 00:03:08,420
If you notice other signals and ports, you have not added proper interfaces using pragmas to the top-
24

25
00:03:08,420 --> 00:03:09,740
function or arguments.
25

26
00:03:12,250 --> 00:03:18,850
After successfully synthesising the code, click on the Export RTL icon in the toolbar to generate 
26

27
00:03:18,850 --> 00:03:24,730
the hardware IP. Now we are ready for integrating this IP into a Vivado project for logic synthesis.
27

28
00:03:27,140 --> 00:03:33,260
In the next lecture, we will create our LED controller project and generate the FPGA corresponding bitstream
28

29
00:03:33,260 --> 00:03:35,640
and examine the design on the Basys3 board.
29

30
00:03:35,640 --> 00:03:36,140
Basys3 board.
30

31
00:03:37,890 --> 00:03:43,890
These are our takeaway messages. Two groups of interfaces should be added to the top-function in an HLS 
31

32
00:03:43,950 --> 00:03:48,840
design 	Argument interfaces ,	And top-function block interfaces.
32

33
00:03:49,280 --> 00:03:55,500
If you don’t add any of these interfaces, the Vivado-HLS considers the corresponding default interface
33

34
00:03:57,960 --> 00:04:04,680
Use the following C function as the LED controller that returns the stratus of the eight input switches, then generate
34

35
00:04:04,680 --> 00:04:07,220
the corresponding IP using the Vivado-HLS.