In the previous lecture, we generated the RTL-IP of our LED controller. 1
Now how can we integrate that in a Vivado project to generate the final FPGA bitstream? 2
In this lecture, I will address this question. 3
Firstly, run the Xilinx Vivado Suite. 4
Then create a new project with the name of “basic_input_output-vivado” 5
Finally, select the Basys3 board as the target FPGA platform. 6
Create a new block design in the Flow Navigator by clicking on “Create Block Design” under the IP Integrator 7
heading. 8
Right-click in the diagram and select “IP settings…”. A separate settings dialog opens, select the Repository 9
under IP in the left-hand side options. Start to add the generated basic-input-output RTL-IP by clicking 10
on the plus button. Then select the corresponding vivado-HLS folder 11
Vivado will search the folder and add the IP to its repository and make that available for design 12
integration. 13
Now, right-click in the diagram and select 14
Add IP. A searchable IP Catalog opens. 15
Find the basic_input_output IP and add to the diagram. 16
Select the input port and make that external. You can change its name from inputs_0 to 17
SW. For this purpose, while the input port is selected, go to the name filed in External Port Properties. 18
Do a similar thing to the output port and change its name to LED. 19
Now we should connect the design ports inside the FPGA to the FPGA pins. Adding a few constraints to 20
the design, will do that. For this purpose, 21
go to the source view and create a new constraint file by pressing the right-click on the Constraints 22
folder and selecting the “Add Sources…” 23
In the Add Source Dialog, make sure that the “Add or create constraints” option is selected. Then press Next. 24
Click on the Create File and choose a file name such as “basic_input_output” and 25
press the OK and Finish buttons. Open the constraint xdc file by double-clicking on the file name. 26
Copy and paste the list of commented constraints provided by the Basys3 board vendor. 27
We should uncomment eight switches and eight LEDs. As the design port 28
names are the same as names used in the constraint 29
file, we don’t need to do any other changes. 30
We are almost ready to generate the bitstream. However, before that, we should do two other tasks. 31
Firstly, go to the design view and right-click on design_1 and select the “Generate 32
Output Products…” option. 33
Then right-click again on the design_1 and select the “Create HDL Wrapper” option. 34
Now click on the Generate Bitstream option in the Flow Navigator View. 35
After the bitstream is generated, we can program the Basys3 board. For this purpose, connect the board to 36
your computer and turn that on. Open the hardware manager by clicking on the corresponding icon under 37
the PROGRAM AND DEBUG in the flow navigator view. 38
Then open the target, 39
the Viviado should detect the board automatically 40
if not check your connections and make sure that the board is ON. 41
Then click on the Program device link and examine the board. 42
This lecture is the last in this section that explained the design concepts and techniques. So the 43
next lecture will give you a couple of hardware designs to be implemented by HLS design flow. 44
This is our takeaway message. To program the target FPGA through JTAG connection, Connect the board 45
to the computer, Then turn on the board, Finally, use the vivado design suite to program the board. 46
Now the quiz for this lecture, 47
Integrate the RTL-IP generated in the last lecture quiz question into a Vivado project and generate 48
the FPGA bitstream. Then program the board and examine the outputs.