In the previous lecture, we designed the traffic light controller in HLS. In this lecture, we use the 1
Vivado-Hlx toolset to map our controller on the Basys3 board. 2
Firstly, create a new Vivado-HLS project and name it traffic_light-vhls. Then, choose 3
a proper path for the new project. After that. 4
choose the traffic_light as the design top function name. 5
Don’t forget to choose the Basys3 board as the target FPGA platform. 6
Download the design files attached to this lecture and save it inside the created Vivado-HLS project 7
folder (or any other desired folder). 8
Right-click on the source folder in the Explorer View in the Vivado-HLS IDE and select the “Add Files…” option. 9
Then go to the folder where you saved the traffic-light files and select the two “traffic_light.cpp” 10
and “traffic_light.h” files and add them to the project. 11
Open the files and examine them. 12
The traffic_light.h 13
is almost empty. 14
I have considered that just for future usage. 15
The traffic_light.cpp file contains five subfunctions describing the five rules 16
that I explained in the previous lecture. And also the design top function. 17
The design top function invokes the subfunctions and generates the outputs. 18
It also has the function argument interfaces. 19
Now we can perform the HLS synthesis process. The synthesis report shows that the circuit delay is about 20
2.934 ns. And the generated hardware is combinational as it uses only LUTs 21
without any memory cells. 22
In addition, the top function arguments are the only hardware ports. 23
After successfully synthesising the code, we can generate the corresponding RTL-IP. Now we should 24
instantiate the IP inside a Vivado project to generate the final FPGA bitstream. 25
Create a new vivado project with the name of “traffic_light-vivado”. 26
Don’t forget to choose the Basys3 board as the target FPGA platform. 27
Create a new block design by clicking on the “Create Block Design” under IP Integrator in the Flow Navigator 28
view. 29
Right-click somewhere inside the Diagram area and select the “IP setting…” option. 30
Then select the Repository option under IP in the list of project setting options on the left. 31
press the plus side and go to the traffic light, all do this project folder. 32
This process makes our traffic light controller RTL-IP available to the vivado design. 33
Now we should instantiate the controller IP. For this purpose, 34
right-click 35
somewhere inside the Diagram area and select the Add IP … option. Search for the traffic_light 36
IP and add that to the design. 37
The design should have four 1-bit input ports and two 1-bit output ports. Make all the ports external. 38
Then you can rename the ports to have more suitable names. 39
Now we should connect them to the FPGA pins. For this purpose, we need to define a set of constraints. 40
You can do that by pressing the right-click on the design_1 under the “Design Sources” 41
in the Sources view and select the “Add Sources” option. In the “Add Sources” dialog, 42
make sure that the “Add or create constraints” option is selected then press next. Then create 43
a constraint file with the name of 44
traffic_light. 45
Double click on the created file under the Constraints folder in the Source view. Now copy the commented 46
constraints provided by the Board vendor and uncomment the required ones. As the design has four 1-bit 47
inputs and two 1-bit outputs, 48
we need constraints for four switches and two LEDs. Modify the ports name in the constraints according to 49
the ports name in the design. 50
Now before generating the FPGA bitstream, First we should generate the output products and then create 51
the HDL wrapper. 52
After that, we can generate the FPGA bitstream. 53
To program the board, connect that to your computer and turn that on. You should see the red power light 54
illuminates. 55
Now in the Vivado-IDE click on the Open Hardware option under the Program and Debug in the Flow Navigator 56
View. 57
Then click on the Open Target link and select the Auto Connect option. The Vivado IDE automatically detects 58
the board and shows that in the hardware list. 59
If you cannot see the board and the FPGA, check the board connected to your computer or turn on the board 60
if you have forgotten. 61
Now click on the Program device link to configure the FPGA. After programming the board successfully, 62
the DONE green light should illuminate. 63
Now we are ready to examine our controller. 64
Each switch corresponds to a sensor, and each led represents a traffic light. Play with sensors and 65
check the lights and make sure your design responds correctly. 66
This lecture is the last in this section that explained the design concepts and techniques. So the 67
next lecture will give you a couple of hardware designs as exercises to be implemented by HLS design 68
flow. 69
These are our takeaway messages. 70
The name of ports in constraints should be exactly the same as the name of the corresponding port 71
in the design. 72
In the current Vivado-HLS description of a design, only arguments in the top-function require attached 73
interfaces. So, the Sub-function arguments don’t need any interfaces as they won’t be synthesised into hardware 74
parts. 75
Now the quiz question. 76
Find the resource utilization of the final design in Vivado. For this purpose, in the Flow Navigator, click 77
on “ImplementationOpen Implemented DesignReport Utilization”