In this lecture, I will take an n-bit binary adder to represent the process of the propagation delay 1
calculation. 2
This circuit is a full-adder design that receives two data bits, an input carry bit, and then after a delay generates 3
the sum and the output carry bits. 4
carry bits. 5
There is a total of 9 paths from inputs to outputs. And If we assume that the delay of an XOR gate 6
is 2ns and other gates require 1ns to generate their outputs, then delays 7
of the paths from a or b to the s output are 4ns. Tthe delay of the cin input to the s output 8
is 2ns. 9
The delays of other paths are also 2ns. 10
So, the longest path in the circuit requires 4ns to propagate the changes on the inputs to 11
the outputs, which means, the output of this full adder should generally be used 4ns after 12
changes on its inputs. 13
An N-bit binary adder can be designed by simply connecting N full-adders sequentially such that 14
the output carry bit of a full-adder feeds the next full-adder input carry. This design usually called 15
the ripple carry adder. This adder utilises the least amount of hardware of all binary adders, but it is the slowest. 16
Each full-adder in the ripple carry adder structure has three paths for data propagation. 17
From a & b inputs to the s output, from carry input to the s output, and from carry input to the carry 18
output. 19
Let’s trace the data along these paths. Let’s assume that the input numbers are available at 0ns. 20
Then after 2ns, the impact of the first bit full adder carry bit appears on s0 and c0. 21
Then after 4ns, the input data changes the values on s0 to sn-1 outputs. 22
However, only the s0 and s1 values are valid, and others will be changed later. 23
At 6ns, S2 and C2 are valid and finally after 2n ns the last sum and carry 24
bits are valid. 25
Two paths determine the last sum and carry bits, and both have 2N ns delay. Therefore, the 26
propagation delay of the whole design is 2N ns. 27
After understanding the logic design structures and their propagation delay concept. 28
Their HLS-based design techniques and approaches would be our next topic. 29
Also, it is obvious that it is not easy for us to calculate the propagation delay for all circuits, 30
especially if they are described in a high-level language such as C/C++. 31
Now the question is: How can we use the Vivado-HLS tool to estimate this delay? In the next 32
lecture, 33
I explain how to use Vivado-HLS to describe a logic circuit and estimate its propagation delay. 34
This is our takeaway message. Serially connected modules in hardware increase the corresponding propagation 35
delay. 36
Now the quiz for this lecture. I have slightly changed the structure of the full-adder and the gates 37
propagation delays in this quiz. 38
Now, what is the propagation delay of the n-bit adder utilises this full-adder?