After understanding the combinational logic and its associated propagation delay, the next question 1
is: How can we describe a combinational circuit in HLS? 2
Let’s take a simple combinational circuit and describe that in HLS. Consider this logic circuit 3
comprised of three gates. 4
The functionality can be described by this logical expression. In order to describe this expression in 5
C/C++, we have two options. 6
We can either use C/C++ logical operators or C/C++ bitwise operators. Whereas logical operators are applied 7
to one-bit logic that can be 1/0 representing true/false, the bitwise operators are applied 8
to a multiple-bit value. 9
I will explain how to use bitwise operators later in this course. 10
Therefore, we can use either of these expressions in HLS to describe our circuit example. 11
We need a function to describe our combinational circuit. 12
The function should have three input and one output arguments. We define a pointer variable for the 13
output argument. Then we should write the logical expression describing the circuit functionality. 14
After that, we have to define the argument interfaces as well as the function block interface. As 15
we are using wires to carry logic values, we use ap_none or ap_ctrl_none as the interface 16
modes. 17
Now we are ready to synthesis the code. 18
After doing the synthesis successfully, the tool gives us a thorough report in which three parts are important 19
for us now: Timing, Utilisation, and Interface parts. The timing part is more suitable for sequential 20
circuits. 21
However, at the moment we are interested in the third column denoted as “Estimated”. 22
This number is an estimation of the design propagation delay. 23
More details about this estimation approach will be described in the “Digital System Design with High- 24
Level Synthesis in FPGA: Sequential Circuit” course. 25
So, the propagation delay of our design is about 0.978 ns. 26
The second part reports the resource utilisation. This part reports an estimation of the number of 27
resources that will be used for implementing the design. 28
The report has five columns. 29
Three of them include memory resources (which are BRAM_18k, FF, and URAM). 30
As we are designing combinational circuits, these resources shouldn’t be used, and their utilisation 31
should be zero. 32
The other two columns that are DSP48E and LUT can be used to implement a combinational 33
circuit. The DSP48E is used for mathematical operators, especially for floating-point data 34
types. 35
The LUTs are used for implementing logical expressions and gates. 36
Notice that our design has only used 6 LUTs. 37
The last part is about argument interfaces which its table has six columns. 38
The first one is the name of the hardware RTL port. 39
The second column denotes the direction of the hardware signals. 40
The number of bits associated with each port is defined in the third column. 41
The next column determines the corresponding interface mode. 42
The fifth column denotes the name of the arguments in the top-function. 43
Finally, the last column shows the type of argument in c, whether it is a scalar or a pointer. 44
In the next lecture, I will practically show how to use the Xilinx Vivado-HLS to synthesis 45
our simple combinational circuit. 46
These are our takeaway messages. The HLS report of a combinational circuit synthesised by vivado-HLS 47
Should not utilise any memory elements. 48
Also, it should not have any clock port in the interface part. 49
Now the quiz question. Complete this code by defining the port interfaces using HLS pragmas.