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After being familiar with designing a simple conventional circuit using Etchells, we should now use

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it before the actual design environment in practice and implement our design in this lecture.

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We are going to use the actual aside to synthesize a simple logic circuit explained in the previous

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lecture and review some practical tips for designing computational circuits.

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First run designing second HLS and create a new project.

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Name the project simple underscore combination's underscore circuit, dash futureless, then choose

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a proper location for the project.

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Name the top function as simple, underscore combination's underscore circuit and choose the basis three

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board as a target FPGA.

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Creating a design fine under the sauce folder in the explorer of you on the left hand side, name it

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as simple, underscore, combination, underscore circuit that CPB.

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Let's try the design example code that we started in the previous lecture.

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It has three binary inputs and a binary output.

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Now we are ready to synthesize the code and examine the report.

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So let's perform that synthesis.

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As you can see, the design propagation delay is about zero point nine seven eight nanoseconds, also

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the result of the hardware is a combination of circuit as it doesn't utilize any memory cell and its

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ports are just simple wires representing the function arguments.

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To better understand the result of the hard work structure, let's have a look at the analysis perspective

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for this purpose, switch to this perspective by clicking on the corresponding icon on the right hand

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side.

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Windows in this perspective are configured to support the analysis of synthesis results, you can use

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this perspective only when the Atlas synthesis complete successfully.

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The analysis perspective interactively provides greater details, the left of the center, Paynesville

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Shuls operations under control of states in the center site design control states are the internal state

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that high level centers as to casual operations into Kalac cycles notice that a combination of circuits

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should perform all its tasks in a single state.

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That's can be our design performs its logical function in a single state denoted by zero.

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By selecting each operation, this perspective shows the timing and data dependencies between the selected

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operation and its predecessors and successors.

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Here we have Terry Reid operations corresponding to the three input arguments in the design, one and

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get.

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They're not is implemented by unexcelled gate.

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And an old gate, finally, there is a right operation to return the result.

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After understanding the synthesized hardware structure, now we should generate the RTL IP and prepare

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for logic synthesis for this purpose.

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You should go back to the synthesis perspective and click on the corresponding icon.

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Now that we have generated our design RTL IP, we should generate its corresponding F.J. with the story

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and examine that on the basis three wars.

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This would be the goal of the next election.

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This is our takeaway message, the analysis perspective in Nevada, HLS provides greater detail of the

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design, including the design structure, timing and resource binding.

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Now, the quiz question generate an IP corresponding to this simple combination of acerca.