After translating our simple combinational circuit design in HLS into the equivalent hardware IP, we should 1
generate the FPGA bitstream and program the basys3 board. 2
For this purpose, run the Xilinx Vivado Suite software. Create a new project and name its 3
simple_combinational_circuit-vivado. Also, choose the Basys3 board as the 4
target FPGA. 5
Now, Click on the Create Block Design link and accept the default design name. 6
Right-click somewhere inside the design area and select IP setting option from the drop-down menu. 7
Then select the repository option and click on the plus sign. Choose the Viviado-HLS project folder 8
created in the previous lecture and press, OK. 9
Then right-click anywhere inside the design area and select Add IP. On the search area, write 10
simple_combinational_circuit and add the IP to the design area. 11
Now select the design ports. You can do that by holding the Ctrl key while clicking on the ports. 12
Then press the right-click and choose the Make External option. 13
You can also change the ports’ names to make them more convenient. 14
Now, we should connect the design ports to some pins on the FPGA. This can be done by adding a few 15
constraints. 16
For this purpose, go to the Source view and right-click on the Constraints folder and then select the 17
Add Sources option. 18
Make sure in the Add Source dialog box, the Add or create constraints is selected. Then in the add or 19
create constraints, click on Create File and choose the simple_combinational_circuit 20
as the file name. 21
Now we can copy the Basys3 board constraints provided by its vendor. 22
Then uncomment and modify the required constraints. 23
We need three switches to provide binary values for our design inputs, and one LED to show the design output. 24
Now we are almost ready for bitstream generation. 25
But before that, right-click on the design option in the Source view and run the Generate Output 26
products option. 27
After that, right-click again on the design option in the Source view and choose the Create HDL 28
Wrapper… option. 29
Now we are ready to generate the bitstream. 30
After generating the bitstream, we can connect the board to our computer and reconfigure the FPGA 31
and examine the design. 32
Up to now, we managed to design a simple combinational circuit and run that on the target FPGA. In 33
our HLS design description, the C/C++ functions play important roles. 34
The next section explains the structure of functions in a design description and their relationship 35
with the structure of the generated hardware module. 36
These are our takeaway messages. As well as the design RTL-IP, we should add the design physical constraints 37
to the Vivado project. To program the FPGA board, Connect the board to the computer, Turn on 38
the board, Use the Vivado IDE to program the board. 39
Now the quiz question. Use the design RTL IP generated in the previous lecture quiz question and 40
program the Basys3 board and explore the design.