How to evaluate our code at the early stages of the design flow and find the possible errors? Simulation 1
is one of the common techniques to answer this question. And a testbench is an essential component 2
in the simulation process. 3
In this lecture, I will talk about the basic concepts behind a high-level C/C++ testbench and its 4
role in the simulation process. 5
Verification is the process, along with the design flow to ensure the final design would satisfy 6
the original features described in the specification. 7
These features can be functional such as output values or non-functional such as timing, security 8
and power consumption, to name a few. 9
A verification process may check the correctness of the design output values, or it can verify and 10
demonstrate the amount of security or power consumption. 11
There are different techniques for verification including 12
Simulation, in which a full software environment is used to evaluate the design description. In this approach, 13
a piece of software called testbench applies some input to the design and the design outputs are compared 14
to with golden models. 15
Emulation, in which the components of the whole system are imported into an environment to evaluate the 16
target design. 17
Formal verification, in which some mathematical approaches are used to prove the correctness of a give 18
design description. Intelligent verification. 19
The focus of this course is mainly on simulation-based verification. 20
A combinational design has n inputs and m outputs. The role of simulation is to apply all possible 21
inputs and check the outputs, comparing with a golden model provided by the design specification. 22
In an ideal case, the number of inputs is two to the power of n (2n), which should be generated during the 23
simulation. A testbench is a piece of software that manages the simulation process. 24
A typical testbench consists of four tasks: 25
Generate inputs, Apply inputs to the design, Apply inputs to the golden model, Compare the outputs 26
of design with that of the golden model. A testbench first generates the inputs, then applies 27
them to the design and golden model and finally compares the results and reports any discrepancy among 28
them. 29
Now that we get the testbench big picture, What is the testbench design flow in HLS? The next lecture 30
handles this question. 31
These are our takeaway messages: Simulation is the verification technique provided by HLS tools 32
A testbench should perform four main tasks: Generate input, Call the design, Execute the golden model 33
and compare the design results with that of the golden model. 34
Now the quiz question. Assume a hardware design has five binary inputs, how many input vectors should 35
a test bench generate to check the functionality of the design?