The question motivated this lecture is: What is the simulation flow in Vivado-HLS? 1
The first step in the synthesis of any design in HLS is to validate its C description. 2
This step is usually performed with the help of a test bench. Writing a good test bench can significantly increase 3
your productivity. 4
Before developing any testbench code for a design, we should know the complete simulation flow in the 5
HLS and its relation with the design flow. 6
By now, our designs were simple, and I have assumed that the designs are correct without any error or bug. 7
So, I only followed and explained the design flow. 8
However, it is not true for a real design as they may have errors. 9
These errors should be found and corrected before the final implementation. 10
For this purpose, the simulation flow should be added to the design flow. 11
Let's have a look at the design flow. A design flow in HLS starts with a C/C++ description of a given 12
design plus its constraints. Then the synthesis process converts the input descriptions into the equivalent 13
RTL description. 14
The IP packaging process generates the final, ready-to-use design IP. 15
To start the simulation flow, we need a test bench file. Then this test bench and the design C/C++ 16
description (without constraints) can be simulated to find any functional error in the code. 17
After correcting all possible errors, the synthesis process can be performed, which generates the corresponding 18
cycle-accurate HDL code. This code can be verified, as well. 19
The process is called C/RTL-cosimulation. 20
In this process, the HLS reuses the C-testbench and apply that to the generated RTL description. In 21
this step, you can check the timing as well as the functionality in a cycle-accurate debugging environment. 22
After doing this process successfully, the hardware IP can be generated. 23
In summary, a design/simulation flow consists of five steps: Developing the design and test bench descriptions 24
in C/C++. Performing the C simulation to find functional errors. Performing the HLS synthesis 25
to generate the corresponding RTL description. Running the C/RTL Cosimulation to check the 26
functionality and timing in a cycle-accurate environment. And generating the IP Package. 27
After getting familiar with the HLS simulation flow integrated into the design flow, now the question 28
is: How can we perform this design/simulation flow in Vivado-HLS? 29
In the next lecture, using a design example, 30
I will answer this question. 31
These are our takeaway messages: To start the C-simulation flow, 32
we need a test bench file. C-simulation checks the design functionality before synthesis. 33
C-simulation is highly recommended before synthesising a design. 34
Now the quiz question. Which sentence is correct Cycle accurate debugging is possible in C-simulation. 35
Cycle accurate debugging is possible in C/RTL-simulation.