Now that we are familiar with the testbench concepts and its coding style, we are ready to use the 1
Viviado-HLS IDE to perform the C and Co simulations in action. 2
Let’s consider this simple combinational circuit, which was explained in the previous section, as an 3
example to implement in HLS and test its correctness. This combinational circuit has three 4
inputs and one output. 5
So its truth table consists of eight rows. 6
We use this truth table as our golden model to compare with the design results. 7
Open the corresponding Vivado-HLS project with the name of simple_combinational_circuit-vhls, 8
explained in the previous section. 9
The project only contains the design source file. 10
Create a testbench source file with the name of simple_combinational_circuit-tb.cpp 11
under the Test Bench folder in the explorer view. Then create a testbench header file with the name 12
of simple_combinational_circuit-tb.h in the same folder. Add the design 13
top-function prototype in the testbench header file. 14
Now in the testbench source file, 15
write 16
the main function that returns an integer value. 17
Define three boolean variables to pass values to the design inputs and a Boolean array with a size 18
of 8 to keep all the possible design outputs. Define another Boolean array with a size of 8 19
to save all golden results extracted from the function truth table. 20
Now, we should generate all the possible design input values. Three nested loops can do this task. 21
Inside the nested loops, call the design function as shown in this code. 22
Use another loop to compare the design outputs with the golden model values and report proper messages. 23
Don’t forget to update the status value according to the comparison results. 24
Now perform the C-simulation and have a look at the report to make sure that the design functionality 25
is correct. 26
You can also perform the C-Simulation debugging process by choosing the Launch Debugger option. 27
This action opens the debug perspective 28
through which standard debugging features such as step execution, insert brake port are 29
available. Also, you can examine the variable contents through debugging. 30
To insert a breakpoint, you only need to click on the blue area next to each desired line. 31
After performing the C-Simulation successfully, we are allowed to run the HLS synthesis. 32
Now we can perform the C/RTL Co-simulation to test the design cycle-accurate correctness. After finishing 33
the simulation, check the report for the successful simulation. 34
You can also dump the design internal and port signal values in a file for showing them through a waveform 35
viewer. For this purpose, choose the proper option in the Co-Simulation Debug dialog. 36
After finishing the simulation, click on the waveform viewer icon, 37
which will open the Vivado for this purpose. 38
Select the design input and output ports to be shown in the waveform viewer. Then check the values. 39
This lecture is the last in this section that explained the design concepts and techniques. So the 40
next lecture will give you a couple of hardware designs as exercises through which you review and 41
master the proposed techniques in this section. 42
These are our takeaway messages. Through C-Simulation we can check the design functionality before 43
HLS synthesis. 44
Through RT/C Co-Simulation we check the cycle accuracy of the design. 45
Also, we can dump the signal values through Co-simulation and examine them in the Vivado Waveform 46
viewer. 47
Now, the quiz question. 48
We know that the final hardware circuit is 49
combinational, but Why does the final waveform viewer contain reset, clock, start and other signals?