In the previous lectures of this section, we understood how to use switch-case software statement to 1
describe decision-making processes and encoder/decoder circuits. Also, we realised how the general form 2
of a multiplexer in hardware can implement these circuits. In this lecture, 3
we take another circuit example called leading one, that can be described using a similar approach. 4
Here, we are going to design a combinational circuit that finds the index of the leading one in a 9-bit 5
binary number. 6
The leading one of a number is the most significant 1 in the binary representation of the number. 7
The circuit should return -1 if the number is zero, which means it doesn’t have any 1 in its 8
binary representation. 9
For example, the index of the leading one in 174 is 7. 10
The index of the leading one in 38 is 5. 11
The index of the leading one in 430 is 8. 12
The index of the leading one in 1 is 0. 13
And finally, the index of the leading one in 0 is -1. 14
This diagram shows a conceptual block diagram for this task. 15
It has a 10x1 multiplexer and a combinational logic that gets the input number and generates the proper 16
select inputs for the multiplexer. 17
As can be seen, the multiplexer inputs are the index value of a nine-bit binary number and -1. Each 18
input of the multiplexer is passed to the output based on the select input value. 19
This second diagram shows another hardware strcure for the same task which consists of four 2 by 1 20
multiplexers and a combinational circuit to generate the select bits. 21
In this structure, each multiplexer determines one bit in the 4-bit binary output. 22
This HLS code shows the if-else statement describing the combinational logic of the leading- 23
one example. 24
The code starts with the most significant bit and returns its index if it is 1 otherwise checks 25
the next bit. 26
After describing the leading one code in HLS, Now we should generate the corresponding FPGA 27
bitstream and examine its functionality of the Basys3 board. The next lecture follows the HLS design 28
flow to generate the FPGA 29
bitstream. 30
These are our takeaway messages. A combinational circuit can find the position of the leading one 31
in a binary number. A chain of if-else statements can represent this circuit 32
Now the quiz question. This code implements a 4x2 encoder; 33
its structure is very similar to the previous example. 34
Find the missing numbers determined by red question marks.