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In the previous lecture, we design the leading one example using the HLS coding style.
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Here, we are going to use the Vivado-HLS toolset to program the Basys 3 board and examine the example 
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in practice.
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Firstly, download the design and testbench files available in the course resources part and save them 
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in a folder on your computer. Then, open the Vivado-HLS GUI.
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Vivado-HLS opens with the welcome screen. 
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Click on the “Create New Project” option to open the project wizard Choose “leading_one-vhls” 
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as the project name and choose a proper path for the project files and then click Next.
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In the “Add/Remove Files” step, insert leading_one as the Top-Function name.
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Click on Add Files and go to the folder containing the design files and add them to the project and 
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then click next.
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Now add the testbench files by clicking on the Add Files option and selecting the testbench files from 
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where you have saved them and then click Next.
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Don’t forget to choose the Basys3 board as the target FPGA platform.
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Let’s have a look at the design and testbench files.
The design header file only includes the ap_int.h 
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header file to the design.
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The design file contains the top function which has a nine-bit integer input argument and returns a 
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5-bit integer as the index of leading-one in the input argument. 
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The chain of if-else statements explained in the previous lecture implements the leading-one functionality. 
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Two pragmas define the design interfaces.
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The testbench header file includes the design file and defines the design top-function prototype.
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The testbench source file has the main() function, which implements the testbench functionality. Another function 
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called find_leading_one_golden is a software implementation of the 
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design which its results are compared against the hardware results. A for-loop in the main function generates 
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all the possible inputs and sends them to the design and compares the results with that of the golden 
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model.  In the case of any discrepancy, 
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the status variable will get the value of -1. Later, 
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the main() function returns the status variable to determine the design failure or success.
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Using the cout object; the code prints the input and result values on the screen for more examination.  
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Now we can perform the C-simulation to check the design functionality.
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As can be seen, the testbench has checked all the possible outcomes successfully. 
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After performing the C-Simulation successfully, we are ready to call the high-level synthesis.
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If we have a look at the synthesis report, we can see that the RTL design utilises 11 flip-flops,
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which means the resulted hardware is not combinational. 
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To find out the reason 
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let’s have a look at the Analysis Perspective, here 
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we see that the design execution requires two steps which means most probably the design propagation 
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delay is bigger than the design clock period constraint considered during the project creation wizard. 
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To change that got back to the design perspective. Then 
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right-click 
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on the Solution1 folder and choose the “Solution Settings” option.
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Now click on synthesis located on the left and on the right area change the period option from 10 
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to 20.
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Now synthesise the code again. 
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This time you should get a combinational circuit which its propagation delay is 10.046ns.
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10.046ns.
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If you go to the Analysis Perspective, you will see that the design only requires one step to finish. 
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To make sure that the resulted RTL design is also correct.
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We can perform RTL/C-cosimulation. 
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The results confirm that the design cycle-accurate simulation is correct.
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Now we can generate the IP and ready to instantiate that in a Vivado-project.
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In order to generate the final FPGA bitstream, Firstly, launch the Vivado Design Suite. From the Welcome
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screen, click Create Project. Click Next on the first page of the Create a New Vivado Project wizard.
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Choose “leading_one-vivado” as the project name and select a proper path 
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for the project,
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and it is a good practice if you check the “Create Project Subdirector” option.
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Click Next to move to the Project Type page of the wizard.
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Select the “RTL Project” option. Select Do not specify sources at this time (if not the default). Click Next. On the Default 
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Part page, under Specify, click Boards and select the Basys3 board.
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On the New Project Summary Page, click Finish to complete the new project setup. The Vivado workspace populates 
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and appears.
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Click on the Create Block Design option under IP integrator in the Flow Navigator. In the resulting 
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dialog box accept the default name and press ok.
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The Diagram window will be open. Right-click somewhere inside the diagram window and select the “IP 
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settings…” option.
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In the setting dialog, select repository under the IP option on the left-hand side. Click on the plus 
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icon on the right and browse the folder of the Vivado-HLS project and press Select.
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The vivado searches the path for any IP ands add that to the repository.
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Then press ok to get back to the diagram window. 
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Then right-click somewhere inside the window and select the Add IP … option.
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In the Search box type “leading_one” and then select “leading_one” and press Enter.
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After successfully instantiating the IP in the design, 
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select its ports and press right-click and make them external. You can change their names with more 
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convenient options.
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Now we should define a few physical constraints to connect the design ports to the FPGA pins.
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For this purpose, go to the design view and right-click on the constraints folder and select Add Resources. 
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Make sure that the “Add or create constraints” option is selected in the Add sources dialog, 
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then click Next.  Create a constraint file with the name of “leading_one”.
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Copy the commented constraints for the Basys3 board provided by the vendor into the created file. 
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Uncomment nine switch constraints and assign them to the a input port of the design.
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Then uncomment five lED constraints and assign them to the design output port. 
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Now select the “Generate Output Products” option.
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After that Create HDL Wrapper.
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Now you are ready to generate the FPGA bitstream. After generating the bitstream successfully, connect the 
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board to the computer and program the board.
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Now lets examine the design on the board.
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After programming the board, as all slide switches are at the zero position, all five output LEDs 
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are ON representing the number -1.
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If we turn ON some of the slide switches, the index of the leading one is shown by the 5 output LEDs.
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This lecture is the last in this section that explained the design concepts and techniques. So the 
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next lecture will give you a couple of hardware designs as exercises through which you review and master
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the proposed techniques in this section. 
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This is our takeaway message. If you expect that an HLS C/C++ code describes a combinational circuit, 
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but the synthesis repost shows FF usage, then the propagation delay of the circuit is higher 
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than the design clock period constraint; 
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so increase the design clock period constraint and synthesise the code again to generate a fully 
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combinational circuit.
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Now, the quiz question.
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During C-simulation, print on the screen the design inputs and outputs by using cout object inside 
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the design file.