Hello and welcome to this course: Digital System Design with High-Level Synthesis for FPGA: Sequential 1
circuits. 2
Are you familiar with C/C++ language and would like to work with FPGAs straightaway without spending 3
months and months learning complex hardware description languages? Then welcome to this course. 4
Are you a software or hardware student who is going to learn the latest technologies about FPGA without 5
spending too much to learn low-level tedious logic optimisation techniques? Then welcome to this course. 6
Are you a researcher with software or hardware background who is going to take his or her research to 7
the next level by accelerating algorithms with FPGAs? Then welcome to this course. 8
I am Mohammad. I have a PhD in Electronics and Computer Engineering. 9
I have been teaching electronics and programming courses in several universities for more than 10 years. 10
I have been doing research on reconfigurable computing for more than 20 years in different universities. 11
I am the author of several conferences, journal and transaction papers published by IEE/IEEE 12
and ACM. 13
Also, I have developed several real applications on FPGAs during my research career. 14
I’ll be your instructor and guide in this course. 15
My first goal is to simplify the new technologies in reconfigurable computing to be used by students 16
and researchers who have no or little background knowledge of FPGA. 17
You may have heard that FPGA design is complicated, 18
yes, it is, if you follow the traditional HDL design flow. However, high-level synthesis design flow 19
makes the FPGA design easy and accessible for a large group of software and hardware engineers. 20
It is my mission here to uncover the high-level synthesis design secrets 21
with a straightforward and exciting approach. 22
We are going to learn, discover and explore the topic of high-level synthesis, HLS. 23
HLS is an entirely new hardware design technology. 24
It is a set of hardware design-flow, optimisation techniques, coding styles, software tools, and 25
debugging mechanisms. 26
HLS is a technology that uses a high-level language such as C/C++ to hide all the traditional hardware 27
design complexities from designers. 28
So, if you are curious about high-level synthesis and don’t know where to start, 29
welcome to this course series. 30
If you are a university or college instructor, lecturer, or professor who wants to add an HLS flavour 31
to the traditional HDL hardware design flow, then welcome to this course. 32
If you want to show that you are clever enough to work with FPGA like a pro just in a couple of days, 33
then welcome to this course. 34
This course is based on the Xilinx HLS technology, including software toolsets and FPGA-based hardware 35
platforms. 36
The technology is well presented, and there are several examples, designs, applications, and supports around 37
it, presented in this course and provided by Xilinx or the HLS community. 38
The technology is already used by several companies to design many commercial devices, including NVIDIA® 39
was able to simplify their code by 5X using HLS  HLS decreased design time by 50 per cent and 40
overall development time, including verification, by 40 per cent. 41
Google Develops WebM Video Decompression Hardware IP Using Technology Independent Sources and High-Level 42
syntheses. 43
In this course, I will use the Basys3 entry-level FPGA board to demonstrate several HLS design 44
techniques. The Xilinx Vivado-HLx software toolset is used to develop logic designs starting from C/C++ 45
code down to the FPGA. 46
If you have a budget of a few hundred pounds and are going to learn very advanced topics on HLS 47
and FPGA, then welcome to this course. You only need to spend a couple of hundred pounds to purchase 48
the Xilinx Basys 3 FPGA board, and all the software tools are available for free via the Xilinx 49
website. 50
This course is the first of its kind that builds the HLS design flow and skills along with the 51
digital logic hardware circuit concepts from scratch. 52
This course is the second of a series on HLS in designing hardware modules and accelerating algorithms 53
on a target FPGA. 54
Whereas this course focuses on sequential circuits, the first course explains the HSL design techniques 55
for describing combinational circuits. 56
In addition, the other courses in the series will explain how to use advanced topics and optimisation 57
techniques in HLS to design logic circuits and accelerate compute-intensive algorithms.