As the HLS design flow is a new topic, its learning requires a step-by-step approach with several examples. 1
The structure of this course is based on this assumption. 2
This course is the second step towards using HLS to design logic circuits and accelerators for FPGA-based platforms, which its focus 3
is on sequential circuits. 4
In this course, I will take the HLS approach to explain the fundamental concepts in designing sequential 5
circuits. I assume that you are familiar with the HLS-based approach to design combinational 6
circuits explained in the first course of this series. 7
This course looks at FPGA from a high-level perspective without going into the low-level hardware details. 8
This course would give you the foundation of using HLS for digital design in Xilinx-based FPGAs 9
to enhance your productivity compared to the traditional HDL design flow. 10
The only prerequisite for this course is the “High-Level Synthesis for FPGA, part 1-combinational circuit” 11
course, and you don’t need to read any specific document. 12
However, referring to Xilinx documents, especially “Vitis High-Level Synthesis User Guide-UG1399” 13
-UG1399” is recommended. For more examples and discussions about the HLS-based design approaches, 14
you can refer to the highlevel-synthesis.com web-log-site or the course Github site. 15
If you have any questions or issues regarding the concepts and codes presented in this course, please 16
refer to the Q&A section. 17
In this course, you’ll learn How to use HLS design flow to implement sequential circuits and how to 18
work with state-of-the-art HLS software tools to implement arithmetic, logic and control circuits on 19
hardware. 20
This is a practical course. Throughout the course, 21
I will explain the concepts of FPGA structure, software tools, HLS techniques, and coding styles 22
to implement several examples. 23
This course comprises four parts. The first part is called prologue, which introduces the course 24
and its structure throughout two lectures. 25
The current video is the second lecture. 26
The second part is called “setup”, 27
which gives a big picture of the HLS for FPGA and its design flow and how to install related software 28
tools and set up the target FPGA board. 29
It consists of one section, including five lectures, from lecture 3 to 7. The third part explains 30
how to develop sequential circuits using C/C++ language in HLS. 31
This part consists of 11 sections and 77 lectures. 32
Finally, the last part puts all explained techniques together to implement three exciting projects. 33
It consists of three sections and 18 lectures. 34
The course parts are designed to cover all classical concepts and techniques in sequential logic design 35
for FPGA implementation. 36
The first project implements a Digital Dice circuit. The corresponding section 37
will explain two different techniques to generate a random number in hardware. 38
The second project implements UART modules to exchange data serially between the Basys3 board 39
and a computer. 40
The last project designs a logic controller to control the rotation of a stepper motor. 41
Each lecture describes a single idea which is presented through a couple of slides. The first slide 42
tells the topic and the motivation, 43
then it follows by a few slides explaining the main ideas and concepts. 44
After that, a slide gives the motivation of the next lecture by posing a question. 45
This slide also creates a conceptual link between two consecutive lectures. 46
Then I summarise the lecture contributions through a few takeaway messages. 47
The last slide in each lecture contains a quiz that helps you to concentrate on the main idea. 48
In this course, I have considered the Xilinx Basys 3 FPGA board as our target platform. Basys 3 is an 49
entry-level development platform based on the latest Artix-7 Xilinx FPGA designed exclusively for 50
Vivado Design Suite. 51
This board is cheap and accessible by almost all students, researchers and individuals. 52
However, the concepts and techniques explained in this course are valid for all other Xilinx FPGAs. 53
What is the structure of the LAB environment that will be used throughout this course? The next lecture 54
will answer this question. 55
The takeaway messages are. 56
This course explains the fundamentals of sequential digital designs using the Xilinx HLS toolset 57
You don’t need to have in-depth hardware knowledge to follow this course 58
Familiarity with the C/C++ language is necessary 59
The “High-level Synthesis for FPGA, part 1-combinational circuit” course is the prerequisite to this course. 60
Download the “Vitis High-Level Synthesis User Guide (UG1399)” 61
document and have a look at its Table of Contents.