What is the harder pipelining technique?
How can it be described in a sequential circuit?
This lecture will define the pipelining, concepts and their usage in designing sequential circuits.
Pipelining is a micro architectural technique to execute tasks at the same time, with some timing overlaps,
let's consider a few tasks that should be executed sequentially to process a stream of data.
These tasks can encapsulate in a function or a loop statement.
Each task needs the results of its predecessor to generate its outputs.
Therefore, they cannot perform in a full parallel fashion.
Examples of this scenario are the assembly lines in a factory.
One way to execute these tasks is the sequential execution in which the system receives new data when
it completely processed the previous one.
In this case, each input data should wait sometimes to be processed.
Another execution mechanism is pipelining in which TASC executions can overlap.
Let's have a look at this execution model first task one receives the first data and gives its results
to task to then while tasked to process the massive data task, one can accept the second data.
In the next iteration, one task, three process the first data, the second task can process the second
data and task, one can receive the third date.
In this scenario, the input data are processed without any delay.
The tasks in the pipeline, micro architecture also referred to as stages.
Pipelining allows the stages to be executed concurrently, each stage does not have to complete all
its operations before it begins, the next stage pipelining is applied to functions and loops.
Let's recall the single cycle sequential circuit design techniques.
In which the combination, all part requires one clock cycle to complete its task, in this scenario,
the design can receive the input data at each clock cycle.
Now, what would happen if the conventional circuit requires more than one clock cycles to finish?
Let's assume it needs to clock cycles.
This diagram shows the timing execution.
As can be seen, the second cannot accept inputs at all clock cycles.
It only accepts input every other clock cycle.
Therefore, the second may miss some inputs or inputs should wait to be processed.
Let's consider the previous sequential circuit that its combination or circuit requires to clock cycles
to do its task.
If it is, why the combination or circuit into two stages or two subtasks with some registers in between,
then we can employ the pipeline execution.
In this case, why the second estate, that is to performs its task, the first stage that is Taiwan
accepts new data.
Therefore, the circuit can receive data at each clock cycle.
The number of clock cycles between two input data in a pipeline micro architecture is called the initiation
interval and for an efficient pipeline, it should be one.
In this case, the initiation interval is one.
How can you describe function pipelining in the next lecture will describe this concept.
These are our takeaway messages, pipeline execution increases the task throughput by exiting and generating
more data than sequential execution.
What?
The initiation interval is the number of clock cycles before the function can accept new input data.
The ideal initiation interval is one.
Now, the quiz question assume that the combination of part of the sequential circuit takes three clock
cycles to finish are the timing diagram of its pipeline implementation with initiation interval of one.