How can we use the function pipelining in using the multi cyclicity counter mentioned in the previous
lecture, this section will explain how to synthesize that into pipelined micro architecture.
This is the last coat of our BCT count.
To guide the sentences to to synthesize the code into a pipeline micro architecture, we only need to
find the pragma in the function body and sentences, too, will take the responsibility of the rest.
Let's see the results in Nevada, Etchells tools.
Create a project with the name of BCT, underscore, counter, underscore pipelining that we do this
and that the design and test bench parties, you can find the files in the resources folder attached
to this lecture.
Let's examine the files.
The design header file has an array containing the seven segment codes.
The design source, fine, contains the BCT counter.
The test bench file contains, of all the calls are designed to function 12 times as we cannot see the
impact of the pipelining in the simulation.
I haven't printed the design outputs on the screen.
Now let's go to the design function and apply the pipeline optimization program in the directive to
right.
Click on the top function and select insert directly.
Then in the white essentialist directive EDITA select the pipeline directive and select the source file
as a destination.
The default value for the initiation interval is one, so you don't need to write anything for this
option after clicking on the OK button, you should see the pipeline pragma under the top function.
Now, let's save the find and perform the simulation and the high level syntheses.
And the report's summary, you can see that the initiation into all of the design top function is one.
Let's go to the analysis perspective.
As can be seen, each function call requires two clock cycles to finish.
However, the design is pipelined with the initiation interval of one, which means it can accept input
in each class cycle.
Now we can perform the RTL CECO simulation and open the way for the viewer.
The way forms confirm the design accepts its input in each click cycle.
Now we can close the window and explore the corresponding article IP.
Created behind the project and instantiate the exported IP.
Then connect the pulse input to a push button switch through the balancer and pulse generator epis.
Then at the constant fight, you can find the IPPs and the constant fight in the resources folder attached
to this lecture.
Generate FPGA bitstream and programmed about.
Now test the design on the wall in contrast to our previous implementation.
You will notice that the design responses to each click on the push-Button.
To better understand the pipeline design behavior, the next lecture will introduce a few performance
metrics for an art hill design.
These are our takeaway messages, I think pipeline pragma to a function can improve its performance
and the rate of accepting input data.
See, simulation cannot show the impact of the pipeline optimization on a function.
Now, the quiz question, what would happen if we change the design top function pipeline pragma as
follows?