In this lecture, we are going to take an example to demonstrate the performance metrics of a pipeline
designed.
IIR filters are the most efficient type of filters to implement in digital signal processing and are
filter receives a sequence of data as its inputs and generates another sequence of data as its output.
This equation shows the relation between elements in these two sequences.
Here is the feed forward, filter order by are the feed forward filter coefficients.
Q Is the feedback filter older?
I are the feedback filter questions.
This diagram shows the graph that is used to represent an air filter in the literature.
Let's assume P and Q are two, then this would be the IRR equation, this equation can be described
in us.
First, we should define the top function with an input and output parameters.
Then we need for static variables to save two samples of input and output data.
The Exxon and and variables represent the current input and output data.
Now we can write our arithmetic expression, then we should modify the state variables and finally returned
output.
Let's synthesize this code, invited specialists and explore the design.
Create a new white to such a project with the name of IRR, that's why the Socialists choose the IRA
as a top function name and select the basis three as the underlying FPGA board.
And the design and test testament to the created project, you can find the files in the resources folder
attached to this lecture.
Let's have a look at what defines the design header file includes the AP underscoring that point and
defines the data type and the five IRR coefficients.
The design file includes the IRR top function explained earlier in the selection.
The test one charter flight includes the design header file and defines the top function prototype.
It also defines the empowerment.
The test bench main function calls, they are designed eight times and pronounced output on the screen.
It also compares the results with the Golden Model.
Now we can run the simulation, the output confirms the correctness of the design functionality.
Let's remove the pipeline pragma and synthesize the code as a design is multi cycle circuit, we should
change the design block interface from AP, underscore, citral, underscore none to underscore Setara
underscore X to be able to run the R TLC code simulation.
This interface adds some extra signals to the RTL module, such as Sarte Ideal, and that helps the
RTL simulation to detect the start and end of each function iteration.
This interface, along with a couple of other interfaces, will be explained in a separate section.
The synthesis report shows that the design initiation interval is three cycles and the latency is two
cycles.
Now let's perform the archaeological simulation and show the waveforms in the revised away from the.
As can be seen, the circuit can accept a new input every three clock cycles and generate the corresponding
output after two clock cycles.
Therefore, the initiation interval is three and the latency of the design is to.
Now, let's apply the pipeline optimization to the design and synthesize the code.
As a nation in turmoil of the pipeline design is one, we can change the module interface to AP, TRL
none or the APC, TRL.
Now let's perform the high level syntheses.
The synthesis report determines that the design innovation turbo is one and it's latency as is still.
Now we can perform the archaeological simulation and check the waveforms.
As can be seen, the design can accept input and generate output in every clock cycle.
As this video is the last lecture in this section that explains the idea and design techniques, the
next lecture will give you a couple of exercises to practice the proposed techniques.
These are our takeaway messages.
The pipeline optimization improves the design throughput, we cannot perform the archaeological simulation
in multi cycle design with Apsey TRL non module interface.
Now, the quiz question, what is the throughput of the Iowa design without pipeline optimization?