After understanding the idea behind the sermon segment driver Succot, let's ride the corresponding
Etchells in this lecture.
As I mentioned before, our CNN segment Driver Circuit consists of two behind IPIS generated by wired
to suchness, signal generator and the driver to display the seven segment numbers.
We start with designing the signal generator and then we design the display driver.
We should refresh the southern segment by concentrate here.
I assume that the refresh rate is 16 millisecond, then we should generate a sequence of single cycle
pulses with a constant period, which is a quarter of the refrigerator.
Therefore, the signal period is four milliseconds.
If we assume that the design clock period is ten nanoseconds, then 400000 cycles fit in a single period.
As you may notice, this signal generator circuit was one of the utility circuits that we designed earlier
in this course, you can find the corresponding source files of this IP in the resources folder attached
to this lecture.
Let's quickly review the IP code invited us wise to such a project with the name of someone underscore
segment underscore signal Dasch why the Socialists and choose the bases to be born as a target FPGA
platform.
Download the design and Test match files from the resources folder attached to this lecture and add
them to the created project.
Have a look at the design here for the macro signal, Andras Calpurnia is defined as the number of clock
cycles fit in a single period.
There are two definitions.
One for the final article IP, which is 400000 and the other for the simulation purposes, which is
10.
The design source, Fine, contains a simple state machine implemented with an if else statement.
And it has been a source file called the design top function several times in fall.
Let's choose the value often for the signal underscore carrier to perform the simulation.
The simulation output shows that the circuit generates a sequence of regular passes for the desired
period.
Now let's perform the sentences and then RTL CECO simulation and have a look at the signal waveforms.
Signal waveforms also confirm the cycle accuracy of our design.
Now for generating the article IP, we should change the signal undisclosed period Macross to 400000.
Now the design should be synthesized again after finishing the high level syntheses export the corresponding.
The display driver circuit receives for visitor numbers and generates the corresponding segment data
and control signals as it is a sequential circuit.
It receives a design clock signal and a result.
If former state a state machine model the driver behavior.
Each state provides data for one and segment, we also need a reference signal to trigger the transition
between states.
Let's write a driver code, each of us.
Curity new white essentialist project with the name of seven underscore segment underscore driver dashboard
to service to the seven underscore segment underscore driver as a top function name.
Don't forget to choose the basis to report as a target of PJ.
Download the design and test files from the resources folder attached to this lecture, add them to
the creative project.
Let's review the cuts first opened the design Heather, it includes AP underscore Intertek hydrofoil.
It also defines a constant area containing the seven segment codes corresponding to the digits from
zero to nine.
Now open the design source file after including the header file, an enumeration type defines the state's.
The design to function contains seven arguments, five inputs and outputs, the function is pipelined
aswell.
We also need to design port interfaces.
A static labor holds the design state according to our design coding style, we define temporary variables
corresponding to outputs and the circuit state.
Now we need a forest state, state machine.
We can use a switch statement to implement that initial state, the circuit sends out the data and control
signals for one seven segment.
The state transitions occur when the state machine receives a high voltage level on the reference signal
as a reference signal provides a single cycle positive pulse.
The state transitions happen regularly.
In the end, we modified the state's register and Outsports.
The test bench had a fight includes the design halophiles and the design top function prototype.
Firstly, the test bench source file defines a match between seven segment codes and the digits from
zero to nine.
This map helps us to generate a more readable output after simulation.
The main function body defines the required variable, then it calls the design several times.
To generate regular passes for the design reference signal to nested loops are used, whereas the reference
signal is zero throughout the inner loop execution, it becomes one in the outer fold.
So using this technique, we generate a regular pulse with the period of 10 cycles that can be examined
during the simulation.
Now let's simulate the code and checked out.
In the printed output, you see the number shown on a certain segment along with the corresponding seven
segment control signals.
Also, we can see that after every 10 repetitions, the circuit goes to the next state because of receiving
a positive pulse on the input reference signal.
Now, let's synthesize the code and check the reports.
If you go to the analysis perspective, we can see that each function execution requires two clock cycles
to finish.
However, the function is pipelined with the initiation into one on one so it can accept input data
on each clock cycle.
Now we can perform the artillery simulation and check the signal waveforms.
As we can see, when the circuit receives a positive level on the reference signal, it goes to the
next state and drives the corresponding southern segment.
Now clears the way for we are an export party, like ready for integrating the design ships and if you
want to project.
Now that we have generated the required lips for our Sun segment Drybar, we should connect them together
any we want to project and generate the FPGA with a stream and check the design on the basis rebought.
The next lecture will do this task.
This is our takeaway message using this loops in the test range, we can generate different types of
periodic input signals for the design on their test, which is described using the technique.
Now, the question, why are there two clock cycles between the rising edge of the refresh signal and
data changes on the seven segment signals?