1
00:00:01,960 --> 00:00:05,050
Now that we have generated the Sun segment, drivers ipis.

2
00:00:06,610 --> 00:00:11,770
How can we integrate them into a we want to project this lecture will address this question.

3
00:00:16,930 --> 00:00:23,410
Create a new Wieviorka Project seven underscore segment, underscore driver dashboard and choose the

4
00:00:23,410 --> 00:00:25,750
basis to report as Target FPGA platform.

5
00:00:45,240 --> 00:00:46,580
Create a new black design.

6
00:00:57,130 --> 00:01:00,610
And they generated Ipis into the river, the repository.

7
00:01:16,490 --> 00:01:18,880
Find the epis and add them to the design area.

8
00:01:28,350 --> 00:01:34,630
Connect the output of the pulse generator to the reference signal of the seven segment driver made to

9
00:01:34,680 --> 00:01:37,410
appear on the clock and AP underscores that external.

10
00:01:43,590 --> 00:01:46,530
Make the four inputs of the seven segment driver IP external.

11
00:01:49,830 --> 00:01:55,020
Also make the output external, modifying the port names if you wish.

12
00:02:29,090 --> 00:02:35,900
Now create a new concern down to the constraints in the resources folder attached to this lecture and

13
00:02:35,900 --> 00:02:39,560
copy its content into the created constraint file individual.

14
00:02:40,680 --> 00:02:46,200
Examine the constraints and make sure that the ports names are the same as your design ports names.

15
00:03:01,960 --> 00:03:07,230
Now create the ideal rapport, then generate output products and finally generate the.

16
00:04:06,110 --> 00:04:08,930
After finishing the process successfully program the war.

17
00:04:37,940 --> 00:04:42,990
Each false light switches on the board determine a digit number, let's play with the ball.

18
00:05:09,830 --> 00:05:16,030
In the next lecture, we will use the seven segment driving tips and design and updown counter with

19
00:05:16,040 --> 00:05:16,760
a load signal.

20
00:05:20,620 --> 00:05:25,930
This is our takeaway message, using the divide and conquer technique to break an application into a

21
00:05:25,930 --> 00:05:29,270
few chips makes the design flow more manageable.

22
00:05:33,190 --> 00:05:39,460
Now, the quiz question, using an integrated logic analyzer, should the sound signal signals in the

23
00:05:39,460 --> 00:05:39,960
Rivaldo?