How can we design an uptown four digit counter with lower than initial value in this lecture will design
such a.
Ardizzone counter has four outputs representing four digits.
It counts from zero to nine thousand nine hundred and ninety nine.
It has two inputs to determine the Counting Direxion account, and it also accept an integer value between
zero to nine thousand nine hundred and ninety nine to initialize the count.
To perform the initialization, we need a one bit input signal called load the counter counts in both
directions.
In this lecture, we described this four digit counter in Atlas, however, to make it operational.
We need a few other IPIS to be integrated into every Wilander project.
We need a certain segment driver that was designed in previous lectures.
We will uSwitch, the bouncer and pulse generator IPIS to connect the up, count down count and load
inputs to push buttons on the basis through both.
When you press the push button, the pulse generator, it generates a single cycle pulse to drive the
corresponding counter input.
Let's design the counter inviter such as?
Create a new white essentialist project with the name of four unrestored digit underscore countered
that she wanted such.
Then create new design and test bench files, as usual.
Open the design, Heather Fine, and include the AP underscore in that.
Openly design source for it, include the design header for it, then define the design top function
with eight arguments for inputs and four hours as only 14 bits represent a number between zero to nine
thousand nine hundred and ninety nine, the counter value variable has fourteen bits.
And the port interfaces also make the design pipeline we need to register to save the counter value.
Also, we need a temporary variable corresponding to the defined register.
Now we can check the load signal, if it is one, we can initialize the counter, then we check the
account signal and if it's one Winkelmann the count to come down here, we should check that down on
the score.
Countering after performing the count main tasks, we should extract the four decimal digits.
Finally, we should modify the counter register, please note that as a design is simple, we don't
need to implement any stage.
Now, open the test bench for include design Heather Fine and another design top function prototype
opened the test by Sourcefire, include the test bench Heather and I assume Feis right.
The main function and defined is not swayable.
Define a set of variables, represent the design arguments.
Now call the design with zeroes onload uptown and downtown signals.
We can generate a set of single cycle pulses on the upcoming put in a nested look while calling the
design.
Now let's perform the simulation.
The output confirms the correctness of their description.
Let's perform the high level syntheses.
Often the analysis perspective noticed that the design is pipelined with the initiation interval of
one, although it's latency is about 17 cycles.
As initiation in turmoil is one, the design can accept inputs on every clock cycle.
After performing the RTL Sea Coast simulation, we can analyze the design waveforms in Rebadow waveform
formatted.
As can be seen, a single cycle on the up count, input increments, the count.
Now we can export the IP to be used in every one of the projects.
Corradini will be one of the project with the name of four underscored Daejeon, underscore counter
that SHIRADO choose the Basis three report as a target FPGA platform.
Create a new blog design.
At five trips to devote vital repository, as shown here, you can find for IPIS in the resources folder
attached to this lecture.
The four digit counter IP into the design area.
Then at the certain segment, Roger Ipis and connect them to the counter IP.
Then the bouncer and pulse generator office and connect them to load up, count and down counting place,
you can change the external port names if you wish.
Now, download the Constantine file attached to this lecture and add that to the blogger project.
Now, synthesizer designed and programmed aboard.
As this video is the last lecture in the section that explains the designing techniques to work with
seven segments, the next lecture will give you a few exercises to practice and master what you've learned
throughout this section.
This is our takeaway message applying the pipeline optimization to a circuit can improve its performance,
even if it's latencies hard.
Now, the police question, what would happen if we remove the pragma natural gas pipeline from the
Cote?