How can we use the interface to detect the key press in a four by four keyboard?
This lecture will address this question.
For the keyboard module, I'm using the digital and pimlott keypad, which is a 16 button keypad, the
keyboard utilizes for rows and columns to create an area of 16 push buttons while driving the column
lines with a low level logic voltage one at a time.
We can read the corresponding logic level voltage on each of the rows to determine which button, if
any, is currently being pressed.
Therefore, our Pyrmont key parts controller will have four states on each state, one column is derived
with logic value zero.
Then Rose will be right.
The key at the intersection of the column and the row with zero value is written as the key.
We should perform this scanning methodology regularly with the frequency of about sixty two point five
kilohertz, which means with the period of 16 millisecond.
Our design consists of two ipis, the first type detects the pressed key and show that on a single cell
and segment display, this IP has three outputs.
One drives the key with columns and to drive a certain segment to display the key.
It also has five inputs, a design clock, a reset, a refresh clock signal, and the status of keyboard
rose.
The second IP generates the pulses with four millisecond per.
Used for the transition between states.
Now, let's describe our design in each of us here.
I will explain the first IP which detects depressed key for the second IP we can use the IP that generates
click refresh pulses described in seven segments section create a new Y to such as project with the
name of Pimlott underscore keyboard dash white essentialists choose the design top function name.
Don't forget to select faces three born as a target FPGA platform.
Artisan conference attached to this lecture and the resources to the creator project upon the design
of their fight, we see it to the constant Arry after including the AP header file.
This area contains the binary index of each key on our keypad, then a constant area represents all
the southern segment codes for the hex numbers from zero to.
Openly designed Sourcefire.
As therefore, as of our design has four states, we define an enumeration type to represent these states.
They're designed to function, has five arguments, two inputs and outputs.
Following the key design approach, the function is parked right now, we need to register to save the
second state.
We also need to register to keep the active column in each state.
Then we define two variables corresponding to these two resistors, these variables keep the intermediate
values temporarily.
We also define two other variables that we need throughout the code.
Now let's have a look at the states in the first set, cold, cold one.
If the input refresh signal is one, then the time slot of this state has been expired and we should
go to the next state called call to.
And the second column should be driven by zero if they state call one time slot is not expired, it
should apply the logic value zero to the first column and read the rules and check which one is zero.
If he has been pressed, the state should return the index of that key.
If no keys pressed, then the no key pressed variables should be activated.
Other states do a similar task.
Finally, we should update the state registers and prepare now.
Now let's synthesize the code and generate the corresponding vivants to.
Create a new one on the project, choose Pimlott underscore keyboard that should be Varnedoe as a project
name, and don't forget to choose bases to be bought as a target FPGA platform.
Create a new blog designed.
At the generated IP and the signal pulse generator to deliver on the IP repository.
Added to Ipis into the design area.
Connect them together and modify the name of external ports, if you like.
Create a new constraint, fine, and the required constraints.
We need a set of constraints to define the clock port.
Also, we should connect the seven segment data and enable signals.
The arrest report can be connected to the center pushbutton.
Finally, we should provide the connections between the design and JCP must signal signal-to-noise.
Now generate the.
I have forgotten to change the clock and reset things, so let's modify them and generate the bitstream
again.
Now we can program the board and examine the design.
This lecture is the last in this section that explained how to work with modern interface in the next
lecture concludes a section by posing a few exercises for you to master the concepts.
This is our takeaway message to detect oppressed key on a four by four mattocks keyboard, we can apply
a low level logic voltage on the column lines once at a time.
And read the corresponding logical level voltage on each of the rows.
Now, the question, modifying the keyboard controller code to make that a single cycle design.