What are the pros and cons of this key design approach, this lecture will answer this question and
give the underlying idea of using the design techniques explained in the rest of this section.
As mentioned previously in discourse, this key design approach provides efficient implementations for
sequential circuits such that they can accept inputs in every class cycle and provide the maximum throughput
available to an application.
The first benefit of the ISKA design approach is performance, if you can design our circuit, considering
the highest frequencies available in the underlying FPGA platform, we can provide high performance
hardware as the second potentially can consume and generate data on each clock cycle.
In other words, the circuit doesn't waste any clock cycle.
The second benefit is the simplicity of the communication between two Hakamada.
Let's consider a data generator hardware module denoted by M1 and a data consumer hardware module denoted
by M2.
If M1 generates its data in each cycle, then M2 will consume that data in the following cycle.
Therefore, there is no need to have any synchronization mechanism between them.
The only constraint is that the data generator should keep the data stable during each clock cycle to
be consumed by the data consuming.
The first drawback is the high clock period, and it is when we cannot design a circuit with a fast
clock signal.
We should increase the clock period.
Consequently, reducing the performance.
The second drawback is unsynchronized data transaction in some circuits following the risky design approach
is not possible.
If it is, science cannot generate their output data or consume their input data on each clock cycle,
then the communication between two modules can be complicated as they do not know when the data is ready
for consumption.
The consumer model may miss some input data or receive invalidate to handle this issue, and explicit
synchronization or hand checking mechanism is required for communication between two modules.
Using the ESC approach to design all circuits is impossible, so some circuits require hand checking
to inform others if they generated data are valid to provide safe data transactions.
What are the handshaking mechanisms available in Etchells and how can we use them?
The next lecture will define the general concepts of handshaking in Etchells.
These are our takeaway messages, this good design approach facilitates a data transaction between two
modules.
There should be a handshaking mechanism between two multiclass cycle modules.
Now, the quiz question, when do we need the handshaking mechanism between two logic circuits?